verilog_work_group
Junior Member level 1
# ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.
# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport
# Runtime, SwiftPLI v1.13
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.
# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport
# Runtime, SwiftPLI v1.13