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Literature on guard rings

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lagos.jl

lagos.jl

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Hi all!

Is there any existing formal literature dealing with the topic of guard rings? I have made a preliminary search on the net and I was unable to find a single reference on the theory behind the design and operation of these by-no-means-trivial though extremely important IC elements. All I found was random advice/explanations from people in forums here and there, but nobody pointing to any books in which this topic is treated more or less formally.

Thanks in advance for any clues to existing references! :D
 

try razavi or alan hastings. I think most books deal with guardrings
 

Thanks for the reply!

Hastings' treatment is good but kind of brief, and doesn't give much examples or practical tips. Do you know of any other references with more examples/practical considerations, like for instance:

-Which types of blocks need to be protected with rings and which don't
-Criteria to decide when it makes sense to protect and when it doesn't
-How to position and dimension the rings
-How to best place the analog and digital blocks with relation to each other
-How are guard rings modelled and included in schematic simulations, both for testing their correct operation and for performing successful LVS tests?

...Any recommended IEEE papers would also help a lot.

Thanks in advance for your help!
 

Ther are many guidelines when its regarding guardrings or placement of dig/analog blocks in a chip.

-> First thing is guardrings do not provide 100% isolation. grings, psub are mostly for lvs cleaning.

-> But still the usual practice is we draw guardrings around sensitive circuits like currrent mirrors or diff amps only.

-> when it comes to analog and digital, at Block level the digital and analog are covered with grings but all dig blocks are grouped and placed at one place and analog on the other so the signal dont cros each other.

-> Usually process like deep nwell and triple nwell are used for isolation.

Also please refer to the below paper on grings...
 

In my view, guard ring is only a mean to provide a reverse bias diode.
Like for double guard ring, there will be 2 reverse bias diode.

For Triple well process, there will be two reverse bias doide for N devices. ( PW-DNW, DNW-Psub).

& Its all depends on the potential, to which you are connecting.
 

guard ring is used to reduce substrate noise due to majority carrier and minority carrier injection.. so two guard rings dependin on the concern.. for mixed signal both is prefered psub and newll to reduce this effect.. in block or transistor lever use psub or nwell guard ring..
 

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