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  1. #1
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    clock glitch

    Hi all,

    I'm designing clock module for ASIC. This is my first experience in clock module design. For synthesis I'm using Design Compiler. I dont know how to give constraints for generated clocks. Can someone give me some info.

    Also is it posible to check with Design Compiler glithes on generated clocks.
    Or the only way is post synthesis simulation?

    Thank you very much.

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  2. #2
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    glitch clock

    Do you mean All digital PLL ?



  3. #3
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    glitches on clock

    It more simple then PLL.

    I have 2 asynchronous clock inputs and 5 clock outputs.

    It is just clock divider. It is not dificult module I understand. But it should be glitch free. I already designed the module and its is working with functional simulation.
    But I dont know will it work after synthesis.



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  4. #4
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    clock gllitch

    Hi,
    If you are using Asynchrous gates (i.e Muller Gates) the concerned module will nor be synthesized and loops will apear. Else, give more details please.
    Regards,
    Master_PicEngineer



  5. #5
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    glitch in the clock

    Hi,

    To be honest I dont know what are Muler Gates :D (if you have some links it will be very appreciated :D)

    I'm using asynchrous gates but there is not any loops.
    It can be be synthesized I tried.

    But I dont know how to check or constraint clock module. How can I be sure that it will work in IC?

    Thanks.



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  6. #6
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    how to find glitches

    Hi,
    Joined Constraining designs doc
    Hope it help.



  7. #7
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    glitch in clock

    Additional materials on Asynchronous Circuits Design:

    http://www.mrc.uidaho.edu/mrc/people/jff/540/index.html



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