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    pcb decoupling

    Hi,

    I'm doing a board with a Cyclone II and i will need to choose decoupling capacitors for it. I'm planning to use FR4 with a power and GND plane. After a fair bit of study it seems like i should use 0.1uF, 0.01uF and 0.001uF low ESL/ESR capacitors. The price of these capacitors widly differ; the AVX caps seems perfectly suited for the job but they are outrageously expensive $2.50 each (!). Pepper the board with these and the design will be expensive...

    Can anyone give examples of good decoupling caps which are more price effective?

    My FPGA has two 16-bit buses and one 8-bit bus (all point-to-point signals).

    Thanks,
    /John.

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    decoupling pcb

    for higher frequencies, use 0402 size capacitors. make your stackup more effective for decoupling: put a gnd plane and a powerplane very close to that surface where the capacitor is. (use thin dielectrics). this way the vias to the planes are shorter, so the mounting inductance is smaller.
    for very effective decoupling in some applications there are LICC capacitors. but i dont think that you need it for an FPGA.

    if you work with xilinx, and you have the HDL project already, the development tool can generate a report about the needed decoupling capacitors/voltage rail. maybe the altera tool has it too.



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    decoupling caps




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    decoupling caps selection

    Thanks avesat and buenos. I pretty much already know that i will need gnd/vcc plane and that i will need three different sizes of caps (0.1uF, 0.01uF and 0.001uF). I will also choose the lower inductance reverse-geometry capacitors (0306, 0508 etc) but what i need to know is what capacitor vendor to choose. The AVX caps are extremely expensive at $2.50 each. Right now i have made a selection but i'm not sure if i need to spend $2.50 on each capacitor or whether cheaper ($0.20) reverse-geometry caps from other vendors will be ok. Some don't even specify impedance curves...

    What caps are being used in "real designs"?



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    pcb power decoupling

    "DMB
    http://home.att.net/~inovak/papers/D...P3_SUN_web.pdf "
    or you can read the writers book. its around 110$
    ( http://www.amazon.com/Frequency-Doma...6855067&sr=8-1 ) and its more detailed.



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    how many decoupling caps cyclone

    Thanks Guys. I got the PDFs and the book. From what i have read so far it seems like a fair amount of live experimentation with the PCB is required to achieve low-Z decoupling over the whole range of frequencies that can cause VCC noise and EMI. In particular, we cant to make sure that the poles of the cap impedance do not coincide which might cause oscillation in the power plane. Any opinion on this?



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    decoupling pcbs

    do you think that the caps cause oscillation in the planes? -i dont think so, but maybe.
    oscillations depend more on the plane geometry, so they are called as "resonant modes".
    you can check result impedance and resonant modes with the cadence allegro PI-option, or with the Ansoft Siwave software.



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    caps for decoupling pcb

    buenos, don't different capacitors have different properties (like ESR) that cause them to resonate with the C and ESL? From what i have read one must pick decoupling capacitors with NOT TOO LOW ESR since they are more likely to oscillate in case the impedance dip coincide with two or more caps? All this makes me believe that the only certain way to make a stable PCB is to actually measure the impedance of the decoupling caps as a frequency is swept into the PCB power plane.

    Or perhaps this is overkill? The fastest parts of my design is an SDR SDRAM running at 120 MHz (driven by a Cyclone II FPGA). Rise times are probably around a ns. I understand that mainly EMI is lowered when using a well designed power distribution / decoupling system?



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  10. #10
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    reverse geometry caps

    i think i also read about bad resonances between neighbor capacitors with different values.

    you dont have to measure, probably you can not do, but you can simulate the Z(f) spectrum, with the mentioned software.

    yes, decaps reduce EMI as well.

    at SDRAM speed, you dont have to worry too much about decoupling, its more critical above this speed. of course you have to design the decap network carefully.



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