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  1. #1
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    Question about density in physical design

    Hi all,

    While doing each stage, after generating this report,

    --------------------+---------+---------+---------+---------+---------+---------+
    | Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    | WNS (ns) -0.237 | -0.237 | 1.586 | 0.681 | N/A | N/A |
    | TNS (ns) -41.568 | -41.568 | 0.000 | 0.000 | N/A | N/A |
    | Violating Paths 698 | 698 | 0 | 0 | N/A | N/A |
    | All Paths 49358 | 25758 | 24098 | 145 | N/A | N/A |
    +--------------------+---------+---------+---------+---------+---------+---------+

    Density: 81.990%
    Real DRV (fanout, cap, tran): (0, 30, 0)
    Total DRV (fanout, cap, tran): (0, 30, 3)

    Consider, I am getting Density as 81.990 at PreCTS section....
    Whether density should not be this much?
    Is ther any limit for density?
    Density is increasing because of more power rails (Stripes) in Core area.???????

    Thanks

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  2. #2
    Full Member level 6
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    Reg: Physical Design

    hi energeticdin

    The density at preCTS stage that u got is little high generally we are adviced to have below 75 % atleast we do tat way .
    well the density is dependend on the area of the chip tat ur designing .. so try to increase teh chip area and the try ..

    Suresh



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  3. #3
    Member level 1
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    Reg: Physical Design

    80% is pushing it. If you want to reduce the density by 5%, then most likely it would require changes in design architecture. Neither synthesis nor floorplanning can reduce the density by that much, unless the implementation is drastically wrong.



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  4. #4
    Member level 4
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    Re: Reg: Physical Design

    firewire2035 Is right. But just for check, have you done scan reordering? If not then, this is a main culprit for such a high density. I faced this problem at initial stage of my career



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