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I want to generate exact 48 MHz clock. Currently i tried to generate by using delays of 20.84, but i am able to generate 47.98 MHz. Hence i thought of deriving it from a higher frequency clock. I am also not sure what higher frequency to select to derive exact 48 MHz clock.Hope u can give me a suggestion now?
Is this for simulation or synthesis? How much jitter can you tolerate? Which device are you using?
Many FPGAs provide DLLs or PLLs that can synthesize various clock frequencies based upon an input clock. For example, with a Xilinx Spartan-3 FPGA you could configure a DCM (digital clock manager) to multiply your 100 MHz clock by the ratio 12/25.
You want a delay of 10.4166666... nanoseconds, but your simulator resolution rounds it off? Is that the problem?
Assuming you have picosecond resolution, you could write a clock generator loop that does this forever:
- delay 10.416ns
- toggle the clock
- delay 10.417ns
- toggle the clock
- delay 10.417ns
- toggle the clock
The result will be exactly 48 MHz, with a picosecond of jitter.
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