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need a clarification Xilinx ISE

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senthilnathan.rajesh

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I've written the AES Encryption and Decryption Algorithm (128 bit block and key size) in VHDL. I am implementing this design in a Xilinx Spartan 3E FPGA with ISE 8.1i. Its taking more than an hour to synthesise. I don't know that it takes this much time.

Can the synthesis time be improved.... how...whether there are any synthesis options I've to set...

Can anybody help?

Thanks in Advance.
 

Check if your design uses memory blocks. If you've used memory blocks to store data and you've written the code for the memory in verilog this will happen. If the memory used is large ISE will take longer time to synthesize it.

To avoid this, use the built-in RAM blocks that ISE offers. This will reduce compile times. You just have to instantiate the memory blocks in ISE using the Coregen and then port map them.
 

Hi,
you can also try to lower the effort of the algorithms. If you change the
effort from medium to low the synthesis process will be completed sooner.
However the area may be increased, but since you only care about the
execution time it will be fine!

pmat
 

Some big designs do take a long time to synthesize. How much FPGA utilization does it report?

Be sure your computer isn't running out of memory. Check your operating system's memory monitor.

I sometimes see extremely slow XST performance if I use a Verilog "initial" block with a "for" loop to initialize a block RAM.
 

My XST synthesis time is really huge !! .. it's been now more than 4 hours and I still didn't get my EDIF !!! .. what can be the reason ??? ..
My laptop configuration is :
1.7G Centrino (Legacy .. got it in 2005).
1GRAM
Linux - CentOS 4
Xilinx ISE 10.1
 

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