Suggestions for doing project about FPGA/PLD in Quartus II

Hello,I'm from China.
Recently,I start doing a project about fpga/pld,and learning the software q u a r t u s II,ModelSim.Is there any suggestion to me(freshman in fpga),thanks!

Any suggestion?

use search to download books about verilog/VHDL

Re: Any suggestion?

thanks.
for several days effort i have finish my project programming and simulating

wiht the software modelSim6

veri good
for share i post out my code the following.

/*************************************/
/*
************************************************************************
名 称:4通道珠片绣(ZPX_N4)板IO的CPLD扩展
作 者:刘金海
创建日期:2007.11.16
修改日期:2007.11.20
修改人员:刘金海
Email:akljh007@163.com
QQ:22080049
备 注:

************************************************************************
*/


module zpx_n4
(
DB,ADDR,WR,RD,
M1,M2,M3,M4,
HALF,RG_OUT,LED_DN,
K_U_D,KN,MD_FUN,RG_IN
);

inout [7] DB;
reg [7] DB_BUF;

input [2] ADDR;
input WR,RD;

/*******************************************/
output [3] M1,M2,M3,M4; //ADDR=1 WR 电机控制信号
reg [3] M1,M2,M3,M4;

output [3] HALF; //ADDR=2 WR 半流控制
reg [3] HALF;

output [7] RG_OUT; //ADDR=3 WR 机头灯输出
reg [7] RG_OUT;

output [3] LED_DN; //ADDR=4 WR 面板指示灯
reg [3] LED_DN;

/********************************************/
input [7] K_U_D; //ADDR=1 RD 汽阀升降
input [3] KN; //ADDR=2 RD 面板信号信入,送片
input [7] MD_FUN; //ADDR=3 RD 组合模式,功能跳线
input [7] RG_IN; //ADDR=4 RD 机头红绿灯输入

reg [3] state; //0~8 状态
reg [2] CT1,CT2,CT3,CT4; //0~7 八拍计数器

assign DB=(!RD && WR)?DB_BUF:8'bzzzz_zzzz; //inout口初始化

always @(RD or WR or ADDR) begin
if(!RD && WR)
case (ADDR)
3'd1:state=1;
3'd2:state=2;
3'd3:state=3;
3'd4:state=4;
default:state=0;
endcase
else if(RD && !WR)
case (ADDR)
3'd1:state=5;
3'd2:state=6;
3'd3:state=7;
3'd4:state=8;
default:state=0;
endcase
else
state=0;

end

always @( state or DB or K_U_D or KN or MD_FUN or RG_IN) begin
case (state)
4'd0: DB_BUF=8'bzzzz_zzzz;
4'd1: DB_BUF=K_U_D;
4'd2: DB_BUF[3]=KN;
4'd3: DB_BUF=MD_FUN;
4'd4: DB_BUF=RG_IN;
4'd6: HALF=DB[3];
4'd7: RG_OUT=DB;
4'd8: LED_DN=DB[3];
default: ;
endcase
end


always @(posedge DB[0]) begin
if(state==5)
if(DB[1])
CT1=CT1+3'd1;
else
CT1=CT1-3'd1;
end

always @(posedge DB[2]) begin
if(state==5)
if(DB[3])
CT2=CT2+3'd1;
else
CT2=CT2-3'd1;
end

always @(posedge DB[4]) begin
if(state==5)
if(DB[5])
CT3=CT3+3'd1;
else
CT3=CT3-3'd1;
end

always @(posedge DB[6]) begin
if(state==5)
if(DB[7])
CT4=CT4+3'd1;
else
CT4=CT4-3'd1;
end


always @(CT1) begin
case(CT1)
3'd0:M1=4'b0111;
3'd1:M1=4'b0011;
3'd2:M1=4'b1011;
3'd3:M1=4'b1001;
3'd4:M1=4'b1101;
3'd5:M1=4'b1100;
3'd6:M1=4'b1110;
3'd7:M1=4'b0110;
default:;
endcase
end

always @(CT2) begin
case(CT2)
3'd0:M2=4'b0111;
3'd1:M2=4'b0011;
3'd2:M2=4'b1011;
3'd3:M2=4'b1001;
3'd4:M2=4'b1101;
3'd5:M2=4'b1100;
3'd6:M2=4'b1110;
3'd7:M2=4'b0110;
default:;
endcase
end

always @(CT3) begin
case(CT3)
3'd0:M3=4'b0111;
3'd1:M3=4'b0011;
3'd2:M3=4'b1011;
3'd3:M3=4'b1001;
3'd4:M3=4'b1101;
3'd5:M3=4'b1100;
3'd6:M3=4'b1110;
3'd7:M3=4'b0110;
default:;
endcase
end

always @(CT4) begin
case(CT4)
3'd0:M4=4'b0111;
3'd1:M4=4'b0011;
3'd2:M4=4'b1011;
3'd3:M4=4'b1001;
3'd4:M4=4'b1101;
3'd5:M4=4'b1100;
3'd6:M4=4'b1110;
3'd7:M4=4'b0110;
default:;
endcase
end

/*
initial begin //仿真激励信号

state=0;
M1=4'b1111;
M2=4'b1111;
M3=4'b1111;
M4=4'b1111;
CT1=0;
CT2=0;
CT3=0;
CT4=0;

HALF=0;
RG_OUT=0;
LED_DN=0;

end
*/
endmodule

Added after 6 minutes:

sorry when i paste the code its Alignment is changed.

the project is about an I/O extend PCB board to connect 51 MCU

if you interest in it ,show me you comment.

Added after 6 minutes:

sorry again,the code notes are written by Chinese.

because i come from China,code notes originally written in Chinese in
my porject files.

i just copy and paste it on the bbs .so That is to say i am a lazy man.