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How to decrease time slacks in Synplify Pro?

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mycentury2003

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Synplify Pro timing

Hi,

I had tried different version of Synplify 7.0, 7.1, 7.2, and 7.3.
I found out the time slacks are getting worst as the version evolves.
The design that once pass the timing constraints in 7.0 (15MHz)
now has slack about -5ns in 7.3.

Is there any additional settings I need to take care of?
 

Re: Synplify Pro timing

the same situation with me,
i don't know what happen or
what new constraint i should need....
 

Re: Synplify Pro timing

Remember that Synplify is just making an estimate of what the timing will be - it's not until you run it through the FPGA vendors PAR tools that you get the definitive answer. Has the PAR timing changed across the revisions?

Also, if you are targetting a new FPGA/PLD architecture it could be that the FPGA vendor has revised their characterisation data of the device, and this is being reflected in the different results you are getting...

J
 

Re: Synplify Pro timing

I found overset the clock frequency can get better results.
 

I suggest you an icremental approach to synthesis... The first time try oversetting the clock frequency (e.g. 200 MHz) and get the estimeted clock frequency. Then do a new synthesis step with a new clock frequency near to the previously found (use a little bit higher frequency than the former found one)
 

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