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  1. #1
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    module sine_cos

    Hi All

    i am after some code to simulate a sinewave input. It will be used as part of a system to simulate the input of a ADC. None of the code has to be synthesizable.

    I have found some code on this forum but i am having a hard time understanding what it does etc. If anyone could expalin it to me that would be great.

    Heres the code

    module sine_cos(clk, reset, en, sine, cos);
    input clk, reset, en;
    output [7:0] sine,cos;
    reg [7:0] sine_r, cos_r;
    assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
    assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
    always@(posedge clk or negedge reset)
    begin
    if (!reset) begin
    sine_r <= 0;
    cos_r <= 120;
    end else begin
    if (en) begin
    sine_r <= sine;
    cos_r <= cos;
    end
    end
    end
    endmodule // sine_cos

    To make a testbench for this code am i right in thinking i will need to generate another module for clk or can it be done with a loop?

    Thank You

    Andrew

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  2. #2
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    Simulation code for sinewave

    That code looks like an oscillator. The derivative of sine is cosine, and by adding a small amount of one to the other, you get oscillation. If you need precise amplitude and frequency, that's not a good way to do it.

    For testbench simulation, try simply using Verilog's $sin() function, maybe combined with $realtime.



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  3. #3
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    Simulation code for sinewave

    Try this testbench!
    ALl you need is connecting them up..



    `resetall
    `timescale 1ns/10ps

    module test_mult;

    reg arst_n;
    reg clk;

    initial begin
    arst_n <= 1'b1;
    clk <= 1'b0;
    en <= 1'b0;

    repeat(2) @(posedge clk);
    arst_n <= 1'b0;
    repeat(2) @(posedge clk);
    arst_n <= 1'b1;
    repeat(2) @(posedge clk);
    en <= 1'b1;
    repeat(1000) @(posedge clk);

    $stop();
    end

    always begin
    #12.50 clk <= ~clk;
    end


    endmodule // convenc_sim



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  4. #4
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    Re: Simulation code for sinewave

    Hi andrew257, ALL,
    I too need sine wave CODE and that should be need to give as input to ADC (analog to digital converter).

    how can i do this using verilog.

    with your posts i understood that you also tried the same thing.if you have the same code please mail me at cruzer2060@yahoo.in

    i will be more thankful to you all.


    THANKS,
    CRUZER



  5. #5
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    Re: Simulation code for sinewave

    I too need sine wave CODE and that should be need to give as input to ADC (analog to digital converter).
    How can you give digital sine wave to ADC? You have to use some function generator (Hardware Equipment) to generate analog sine wave.



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