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dual port fifo with two different clock input

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I know this issue is kind of old? but anyone can provide some suggestion
to design a dual port fifo with two different clocks input ?
 

Also Xilinx many App Notes about different usage of its dual port RAM as (FIFO, Bus Width converters, ..etc) you certainly will find good ideas help your topic.
 

this webpage has some good resources about asynchronous fifos
\hxxp://www.geocities.com/deepakgeorge2000/
 

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