VHDL dual port RAM help

dpram vhdl

i use coregen to generate a dual port Ram...

i wrote Data into AddrA 0,1,2,3,4,5,6,7,8,9

but when i read the data from AddrB...

AddrA 0 = AddrB 3 instead of AddrB 0
AddrA 1 = AddrB 4
AddrA 2 = AddrB 5
.
.
.
.
AddrA 9 = AddrB 12

is like..the data doesnt match wif the address array....
any idea why?

dual port ram vhdl

is there a delay when i write into the address array or when i read from the address array...........??

vhdl dual port ram

Hi,

Can you upload the code? It will be useful to solve the issue early..

Regards,
Kanags

vhdl dpram

u are using dual port....

1. it means u should have to read/sample data on both edge of cycle...
are you doing that ???

2. set all data bits alternate ex...0101010
the see the delay on scope

3. chk the property of core generator..
specailly the big/little endian ...

4. use the low frequency first then increase after completing test..
5. chechk the varialbe used for reading...

dualport ram vhdl

tom_hanks

Dual port does not mean data is transferred on both edges of the clock. It means that the memory array has two independent read and/or write ports. You're thinking double data rate memory.

double port ram vhdl


yes i have mistaken

ram+in+vhdl

heres the program....i zipped it

Port A to Write and Port B to Read...

ramb16_s36_s36

Hi,

Following is code which i used to make true dual port ram forvirtex_II. This one works for synthesis nad simulation. You can also do similar for you fpga target.

RAMB16_S36_S36 is the virtex-II true dual port ram.

regards,
ram
========================
/*******************************************************************************
* All rights reserved. *
* Design Name : dpram *
* Function : Dual port Ram for Xilinx vertex2 *
* Coder : Mogambo *
*******************************************************************************/

module dpram_32_512 (
ena, enb, wea, web, clka, clkb, addra, addrb, dina, dinb, douta, doutb
);
input ena;
input enb;
input wea;
input web;
input clka;
input clkb;
input [8 : 0] addra;
input [8 : 0] addrb;
input [31 : 0] dina;
input [31 : 0] dinb;
output [31 : 0] douta;
output [31 : 0] doutb;
wire fix_0;
wire web_n, wea_n;
assign fix_0 = 1'b0;
assign web_n = ~web;
assign wea_n = ~wea;

//defparam RV.SETUP_ALL = 312;
//defparam RV.SETUP_READ_FIRST = 312;

RAMB16_S36_S36 RV (
.CLKA(clka),
.CLKB(clkb),
.ENA(ena),
.ENB(enb),
.SSRA(fix_0),
.SSRB(fix_0),
.WEA(wea_n),
.WEB(web_n),
.ADDRA(addra),
.ADDRB(addrb),
.DIA(dina),
.DIPA({fix_0,fix_0,fix_0,fix_0}),
.DIB(dinb),
.DIPB({fix_0,fix_0,fix_0,fix_0}),
.DOA(douta),
.DOPA(),
.DOB(doutb),
.DOPB()
);

endmodule
===================================

ram inout port vhdl

sorriex..i dun realli understand the codes given by Ram

i read this from some forum....issit impossible to write and read on the same address location?

vhdl two write ports

Which coregen RAM core are you using? Check its data sheet document for an explanation of what happens if you attempt to read and write simultaneously to the same address. I would expect the write to succeed, but the read may be corrupt. The data sheet should also answer your other questions.

true dual-port ram in vhdl

ermm...if i use If loop......and i need to put in 2 condition.....how should i write?