Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Implementing tri-state buffer at the bottom hierarchal block

Status
Not open for further replies.

khaila

Full Member level 2
Joined
Jan 13, 2007
Messages
121
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Activity points
2,105
What is the functionality different or the implication of next two situations:
1. An output of OR'gate that is feeding TRI_STATE buffer and that buffer is feeding a PIN output.

2. OR'gate output is connected directly to a PIN output while OR'inputs are connected to two independent TRI_STATE buffers.

I know first option is more "economized" but the second option is more functional.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top