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Questions about CDL netlist with Vsource

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starrinesss

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cdl netlist procedure

how can I extract a Vsource into netlist use CDL method?
there is a voltage source vdc in my sch but doesn't shows up in the CDL netlist, is this a cadence problem or I miss some key setting?
 

cdl netlit procedure

vsource no CDL view.
 

aucdl res $sub=

but actually, there is a view named auCdl in analoglib for every vsource, such as vdc, vsin ..so, that's the config of cadence?
 

The auCdl netlisting procedure supports the following devices: FET, CAP, IND, DIODE, BJT, MOS and RES.
But, why do you want to translate vsource into auCdl netlist?
 

because my sch is big and need several different stimulations for different port.
and I'll use hsim as the simulator, so I need to transform a virtuoso sch to a spcie netlist, that's why I need an entire netlist contains vsources.
 

But every simulator has own sources, and distinctly. Even if you translate successfully, the simulation is unsuccessful probably.
 

o. but I need only a standard hspice netlist, so may the hspiceD simulator could generate a proper netlist.
 

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