Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog code error: unable to determine top module

Status
Not open for further replies.
M

moustafaali

Member level 2
Joined
May 14, 2007
Messages
46
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
cairo,egypt
Activity points
1,563
salam alikom
hello
i'm new in verilog and need test semple project using logsim
this is the code
/////////////////////////////////////////////////////////////////////////////
//counter project
module counter (clk, reset, enable, count);
input clk, reset, enable;
wire clk, reset, enable;
output count;
reg[3:0] count;
always @ (reset)
begin
if (reset == 1) begin
count <= 0;
end
end
always @ (posedge clk)
begin
if (enable == 1) begin
count <= count + 1;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////
and this is the error appeared
/////////////////////////////////////////////////////////////////////////////
# compilation completed
** Error ** unable to determine top module
 

Re: verilog first code

Hi,

Actually, there are multiple errors here.

Code: 
//counter project
module counter (clk, reset, enable, count);

input clk, reset, enable;
wire clk, reset, enable;
output count;    <------- output [3:0] count;
reg[3:0] count;

always @ (reset) <--------I believe u r trying to do async reset not good coding style 
begin
if (reset == 1) begin
count <= 0;
end
end
always @ (posedge clk)
begin
if (enable == 1) begin
count <= count + 1;
end
end
endmodule

Below is the correct way to code it:

Code: 
module count (clk, rst, enable, cnt);

input  clk, rst, enable;
output [3:0] cnt;

reg [3:0] cnt;

always @(posedge clk or posedge rst) // async active high reset
begin
     if(rst)
           cnt <= 0;
     else if(enable)
           cnt <= cnt + 1;
end

endmodule

You can learn verilog from any verilog books. One suggestion is Samit Planitkar (sorry if wrong spelling). U can actually search in this forum.

Hope it helps.
 

Re: verilog first code

no no it is right
all the problem that i didnot make project:D:D:D:D
excuse me this my first project
by the way this sentence is right
and thanks for your modification it is very suitable not large as i write and thanks also for the illustrate of the difference between the sync and async
 

verilog first code

I think good coding style is more important
 

Re: verilog first code

may i know that ur code that have a testbench.. i needed to do for my counter.... hope that ue can help mie... thank you advance....
 

Re: verilog first code

hi anyone there can help...i need your testbench... thank you
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top