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What is attribute and allias in VHDL ?

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master_picengineer

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What is attribute and allias in VHDL.
Please provide an exemple.
Are these instructions recognized by synthesis tool like DC ?
Thanks.
 

Question in VHDL

ATTRIBUTES ARE NOTHING BUT JUST LIKE CHARACTER OF PERSON.,HIEGHT, HAIRSTYLE ETC.
 

Re: Question in VHDL

Hi

Please see this file. it describes what you want. also other features of VHDL. search the file for "ATTRIBUTE" and "ALIAS".
it includes helpfull examples.

regards
 

Re: Question in VHDL

**broken link removed**
 

Re: Question in VHDL

An attribute is a user-defined label you can attach to anything. Usually the synthesis tool will just take this label and pass it on in the netlist.
This way, you can control certain routing tools through strategically placed labels.
Code: 
attribute preserve_signal : string;
...
signal mysig : std_logic;
...
attribute perserve_signal of mysig:signal is "TRUE";

This glues a label of string type, called "preserve_signal" onto the signal mysig. When the synthesis tool sees this, and if the "preserve_signal" label is a special option for that synthesis tool, it may interpret it as a hint not to optimize away a net.
A label "black_box", when put on a component, may instruct the synthesis tool to preserve it without synthesising the contents.
So the meaning of labels (attributes) is tool-specific. A VHDL-standardized user attribute is called "foreign" (a string attribute) and is used to create external DLL calls for the "FLI" (foreign language interface).
Code: 
attribute FOREIGN of myfunc:function is "myDLL:my_c_function";

Similarly, you can put
Code: 
attribute LOC: string;
...
attribute LOC of input1 : signal is "P13";
and the Xilinx routing tools will recognize the LOC label as the "location" constraint to put the signal on pin P13. Assuming "input1" is defined in the top entity port of course.

There are also the built-in language attributes, that begin with apostrophe '
They are used to ask certain properties of types, signals, events and arrays. Most of them are not synthesizable, but a lot are. 'event is used for clock edges, 'high, 'left, 'pos, and their opposite counterparts are very useful for writing code that automatically scales with the size of the vectors.

Aliases introduce synonym names. Like
Code: 
signal statusregister : std_logic_vector(7 downto 0);
alias status_done : std_logic is statusregister(5);

Now status_done is a synonym for statusregister(5).
 

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