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Glitch detection in RTL using Spyglass/Conformal/Debussy

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sam536

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glitch detection

Hi,
I have circuit as attached here. Is there any way we can find out the glitch curcuit in RTL using spyglass/conformal/Debussy or etc. I am looking for schematic to see for my design where ever glitch may occur.

Problem :
There are Three FFS(FF1,FF2,FF3). FF1 is driving with clk1 and FF2 and FF3 are driving with clk2. The input to the FF3 is from FF2 as well as FF1 as shown in the fig. Can i find such type in RTL and report it with any tools.

Your inputs are appreciated.

Regards,
Sam
 

Re: glitch detection

This is a "Clock Domain Crossing" scenario...
You can use Spyglass & its clock domain crossing rules or
Mentor's 0-in CDC for analyzing such circuits... 0-in CDC does a very analysis... it has a whole lot of built in rules which are meant for clock domain crossing checks...

-Harish
 

Re: glitch detection

Harish, Thanks for your inputs.
My Question is not regarding the clock domain crossings . I need to know , how to find out the glitches as shown in the figure. Signal coming from the Reg1 and Reg2 are combined and leading towards to Reg3. I need to know , any tools are able to find out/generate the schematic for this.

Regards,
Sam
 

Re: glitch detection

HI

You can not have this type of design in actual Design .

In clock Domain passing the signal passing from one clock domain to other cannot pass through Combinational logic .

It has to a registered signal .
 

Re: glitch detection

Thanks ashgun. Yes You are corrct. But the Question is there any way to find glitchy logic using EDA tools, which is shown in schematicc?.

--Sam
 

Re: glitch detection

I guess Clock_glitch04 rule in SpyGlass should be able to catch such situation, they have other glitch catching rules as well. These rules are part of SpyGlass-CDC.

Regards,
Narayana
 

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