Help regarding sdf back annotation

Hi everybody,

I am stuck in a very odd spot in my tool flow. I am working on some asynchronous modules which is working with synthesized synchronous module. i am able to generate the sdf file using Design Compiler, but i am not able to back annotate this sdf for testing in Modelsim. I have tried it with NC-Verilog, but its also not using the sdf file, instead for both i am getting the unit delay model based simulation results.

I wanted to ask you whether the version of sdf file and the support for that sdf file version in the tools can be an issue as i am using Design compiler version 2006.12 and my Modelsim version is 5.7c.

If anybody wants to share the steps which he/she follows for backannotation with some commands then that will also be a great help.

Regards

Vikas

nc-sim should be simple or i may be accustomed to it.
use the auto_sdf switch in ncelab command and that will take care of everything.
u need not compile it in ncvlog command

Thanks for you reply. I was able to solve the problem in NC Verilog as i didnt know that i had to use ncsdfc command to convert the sdf file and then make a command file to import the new sdf file into the design.

Vikas