ayza1505
Newbie level 3
converting vhdl code into verilog
i tried to convert this file into verilog but it cant works!!there's a few things missing.i guess so.pls help me...
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Entity d_ffdelay is
port (clk,resetn,d_in: in std_logic;
d_out : out std_logic);
end;
Architecture rtl of d_ffdelay is
signal s: std_logic;
begin
process (clk,resetn)
begin
if resetn='0' then
d_out<='0';
elseif clk'event and clk='1' then
s<=transport d_in after 20NS;
d_out<=s;
end if;
end process;
end
i tried to convert this file into verilog but it cant works!!there's a few things missing.i guess so.pls help me...
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Entity d_ffdelay is
port (clk,resetn,d_in: in std_logic;
d_out : out std_logic);
end;
Architecture rtl of d_ffdelay is
signal s: std_logic;
begin
process (clk,resetn)
begin
if resetn='0' then
d_out<='0';
elseif clk'event and clk='1' then
s<=transport d_in after 20NS;
d_out<=s;
end if;
end process;
end