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Setup - the minimum time before which data must be stable before clock transition
Hold time - the minimum time after which data must be stable after clock transition
Set up and hold is related to input signal and clock edge, not output.
If you input meets these requirement then you will get a valid output.(after clock to Q delay of flop from clock edge).
Setup time is the time for the input signal to get loaded in to the latch, before latch gets trigerred by the active clock edge.. so that the signal can be samled properly.
Hold time is the duration for which the latch looks at the input after the active clock edge, so that it can get sampled properly... any signal change after the hold time won't be available to the output until the next clock edge.. so, signal can change after the hold time...
setup time is how early the data should be present before the clock edge arrival.This should be before clock.
where as hold time is how much time the data to be held after the clock edge arrival.
I believe it is better to know how set-up and hold time will come into picture than blindly remembering setup is before clk edge and hold is after clk edge
I recommend to read how the edge triggered flip-flop works in digital design by moris mano
when dealing with flops, the data should be stable for some period before and after the clock trigger occurs. the period for which the data shld be stable before clk edge is called setup time and tht after clock edge is called hold time
the attachment is a part of STA ppt loaded by Fayez Mohd
set up and hold time are the most important parameters when we are dealing with a synchronous design.
because the sanity of the input wrt to clk is very imp bcoz these parameters are applicable only for inputs.
for setup time and hold time violation in think there r two equations to fullfill the correct operation of circuit. so both r important for max.. clock frequency.
equations are..
Tc-q + Tsetup + Tcskew + Tcomb <= T (setup)
Tc-q + Tcomb - Tcskew >= Thold (holdtime)
genrally in designs setup time is greater than hold time and always we talk hold time in terms of negative slack
The max cycle time is-- the clock to Q delay of flop1 + clock skew of flop1 + the maximum propagation delay of combo logic + the setup time of flop2.
Hold time is not considered in calculating clock frequency.
Ideally hold time of a flop should be zero. For eliminating hold time violations, the lock to Q delay of flop1 + min prop delay of combo logic - clock skew to flop2 should be greater than the hold time of the flop2.
Best way to thoroughly understand Setup time and Hold time is to read a good textbook. I'd recommend chapter 7 of CMOS VLSI Design by Weste and Harris available online on Google books.
set up time is the time before which data should be held stable before the rising edge of the clock
Hold time is the time for which the data should be held stable after the rising edge of the clock so that it is correctly recognized by flop.:roll:
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