Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with Altium Designer

Status
Not open for further replies.
altium logo

The information you need to provide to a fab is the same, regardless of what EDA program you use.

Gerber files are also called photoplot files. They are used to produce plots through which photosensitized panels are exposed to light. They contain no intelligence about the design except the exact location of lines and pads on whatever layer for which they are generated. To provide the rest of the information necessary to manufacture a board, you either have to create a mechanical layer containing the data, or provide a text file with the information. You also need the drill file to define the location of drilled holes.

1. Normally, you put all of the necessary mechanical information on the "Drill Drawing". In AD, this is a defined layer by that name. If you are going to have an assembly house assemble your board, you will need to provide other mechanical layers to them with information that helps locate all of the components.

2-3. You need to generate a Gerber file for each of the copper layers/planes in your board. You should also generate a Gerber file containing the board outline - this will be used by the fab for routing the board from their panel. You will also need the Drill Drawing Gerber layer upon which you have written all of your specifications for the board - material type, dimensions, stackup, and any other information you want used to produce your board exactly as you have designed it. Finally, you need the drill file so the fab can drill the vias and thru-hole pads.

4. It is a good idea to specify which Gerber file goes with which layer. Every EDA program does it differently. For example, Allegro produces files with the numerical sequence of the stackup in the name and the extension ".PHO". The numerical sequence starts with the top silkscreen, and continues down through the solder mask, top, inner layer 1, etc. Your fab may not necessarily be used to the way your EDA software names the files - it's best to tell them to be sure.

5. The "CAM" file produced by CAMTASTIC in AD6.7 is a summary file that is readable ONLY by CAMTASTIC. Every cam editor has its own proprietary file format for storing a summary (composite). Your fab would have to have the same CAM editor you use in order to open that file. It is NOT intended to be a fabrication file. Stick with Gerbers and Drill files, or ODB++ (an alternative fabrication file).

6. Where you set your user origin doesn't matter. When you generate your Gerber files, you are given the choice of having the Gerber reference the relative or absolute origin.

7. The IPC Standard your fab is talking about is probably IPC-2221 "Generic Standard on Printed Board Design". I think the section to which they are referring is: "When conductors of melting metal have a width larger than 1.3 mm, the design of the conductor shall provide a relief through the metal to the base laminate substrate. The relief should be at least 6.45 mm2 in size and located on a grid no greater than 6.35 mm. When conductor areas of melting metal are to be left uncovered, the design for all class boards shall provide that the solder resist shall not overlap the melting metal by more than 1.0 mm."

Note that unless your board needs to pass some sort of acceptance testing as a commercial product, the above standard is optional. Nothing says you MUST follow the standard.

8. You should do the tenting in your original PCB file. It can be done in CAMTASTIC, but it's a lot of manual work. The solder mask Gerber is a negative image - in other words, mask is applied everywhere there is not an object on the plot. You would have to remove all of the objects corresponding to mask openings in order to tent from the Gerber file. In the PCB Editor, tenting is a simple instruction in the pad or via dialog, and can be generated globally.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
altium importing logo

which IPC standards do I need to know in PCB deaign?
 

turn off thermal on vias altium

If you intend to design boards to IPC standards, you should be familiar with at least:
IPC7351A - Generic Requirements for Surface Mount Design and Land Pattern Standard
IPC-2221 - Generic Standard on Printed Board Design
IPC-2222 - Sectional Design Standard for Rigid Organic Printed Boards

It helps to also be familiar with what can go wrong in fab that disqualifies a board. Some of the defects can be prevented if proper allowances are made when laying out the board. The standard that covers board inspection is:
IPC-A-600G - Acceptability of Printed Boards
There are pictures of actual boards used to show the problems that can arise.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
altium designer known issues

is IPC-A-600G upgrading to IPC-A-600D or is new one? are doc of those standards free or I need to buy them? what IPC-4101/42 stands for?
 

laptop with graphics cards for altium

Johnson said:
is IPC-A-600G upgrading to IPC-A-600D or is new one? are doc of those standards free or I need to buy them? what IPC-4101/42 stands for?

IPC-A-600G is a newer version of IPC-A-600D. Like most standards, they are not free. You have to buy them from IPC ( **broken link removed** ).

"IPC-4101 - Specification for Base Materials for Rigid and Multilayer Printed Boards" - the "42" refers to a section in the standard for a particular kind of board material. You can see a table of the materials defined by IPC-4101 at:
**broken link removed**

If you want to see a table of all the IPC standards, there's one at:
https://www.ipc.org/4.0_Knowledge/4.1_Standards/SpecTree.pdf
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
gold plated pad altium

Regarding the drill drawing plot, another plot exist at: file -> fabrication outputs -> gerber mask -> (TAB #3) drill drawing. Is it same as other direct generated files? or contain new info?

Dealing with PCB issues, fabrication notes, and also assembly note I found this book useful:

"PCB Designers' Reference", by Chris Robertson.

and chapters on

"PCB Handbook" by: Clyde F. Coombs.

Do you recommend other books or tutorial if exist? Also reference design of ML40X on Xilinx web site contain good information. Now I am looking for a sample fab note in AD projects!
 

altium recommended graphics cards pads

Using the tab under "Fabrication Outputs" is just another way of printing the Drill Drawing layer. There's no additional information available by using this menu entry.

The two books you listed, especially Coombs, are the ones I would have recommended.

You can see an example for one way of presenting manufacturing notes in the AD example "C:\Program Files\Altium Designer 6\Examples\Reference Designs\SpiritLevel-SL1\SL1 Xilinx Spartan-IIE PQ208 Rev1.01.PcbDoc". Your notes don't have to be that complicated, but you can see the sort of information that a fab may be interested in.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
excellon drill altium

the fab note in recommended design is generated externaly, do you which tool is used?
is PADS, able to generate layer stack-up and drill table legend automatically?
 

+altium +manufacturing +check

As far as the layer stack-up, you can go to tools - layer stack-up legend to place the stack-up on any layer you want.
 

print negative from altium designer

Johnson said:
The tool is very slow and get near to 1G ram, for a design that contain only 2 X 1148pin FPGA and 16 X PQFP100 with few other cap and res.:cry:

Is it true to say that tool is not suitable for component count more than 512?
If so, what other tool do you recommend?

Could it be a problem with your video card? I have a 2GHz dual core laptop which has Nvidia graphics card and 1G ram but it still runs too slow and also stalls occasionally. Now I am using a 2.6GHz desktop with 2G RAM and on-board graphics card and it works smoothly.
 

altium designer slow

Johnson said:
the fab note in recommended design is generated externaly, do you which tool is used?
is PADS, able to generate layer stack-up and drill table legend automatically?

I think I mentioned in a different thread that you can place a drill table automatically using AD by placing the special string ".Legend" on the drill drawing layer. You can also place a stackup drawing on any layer you want using Tools>Layer Stackup Legend.

I only provided the example of the SL-1 board to show you what sort of information is needed to give a complete description of the board to the fab. Each designer has their own favorite or company required way of providing the information. There is another example available online from a different EDA package: https://www.datacircuits.com/docs/Fab Drawing Sample.pdf

PADS does not automatically place the drill table or stackup on a drawing layer. You need to design that for yourself. There are scripts avaiable for PADS that help generate this type of information display, but it is not native in the program.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
excellon drill file viewer altium

in order to have a e-testable PCB, which rules must be obeyed in design phase? is there any standards related to this issue?
 

altium show layer laptop

If you mean bare board testing, there are no limitations on the design of your board. Many fab's use a flying probe tester for bare board testing, and they generate an IPC-D-356 test file from the Gerber files to program their tester. You can also supply the IPC file from AD by going to "File>>Fabrication Outputs>>Test Point Report". For more information about the IPC file format, see: **broken link removed**

If you are talking about a board that is testable when populated, there are some things you have to keep in mind. You may need to add testpoints (bare surface pads) to make connections to some components testable. Most board testers can't probe a surface pad that has a component lead soldered to it - they need a test pad. Some testers need the test pads to be on a specific grid - they can only resolve certain distances on the board. It all depends on what kind of tester is going to be used (i.e. bed-of-nails, flying probe, etc.) There's no general set of guidelines that apply. It all depends on how extensive the testing needs to be (all nets, just critical nets, statistical testing), and what tester is going to be used.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
via altium bga middle layer

- Regarding the stack-up, some uses 1oz and other 1/2oz for internal plane layer, and 1/2oz for other layers in both case. What is the difference between these two theckness in terms of PCB issues? Is it a SI issue? or related to lithography phases? Also the plating of external layer with extra foil(making it thicker, may be) is another question.

- After receiving the fabricated PCB, and befor assembly, which inspections do I need to do?

- What is the difference between HASL and tin-lead as the finishing layer?
 

logo,altium

Johnson said:
- Regarding the stack-up, some uses 1oz and other 1/2oz for internal plane layer, and 1/2oz for other layers in both case. What is the difference between these two theckness in terms of PCB issues? Is it a SI issue? or related to lithography phases? Also the plating of external layer with extra foil(making it thicker, may be) is another question.

- After receiving the fabricated PCB, and befor assembly, which inspections do I need to do?

- What is the difference between HASL and tin-lead as the finishing layer?

1/2oz copper is typically .7mil thick.
1oz copper is typically 1.4mil thick.

The difference is the thicker one has more current carrying capacity at the same track width. Its not really a SI issue. Most fab houses I've dealt with by default have 1oz inner and 1/2 outer. You can go with 1 oz outer if you want, it really wouldn't make a difference. Now if you have impedance control you have to recalculate your width based on the new thickness of the copper.

Hopefully none as thats the board houses job. With a multilayer board the only practical thing you can do is just a visual inspection.

HASL-hot air solder level is typically lead free.
tin-lead contains lead and is not RoHS compliant.



Regarding the speed issue..


With Altium Designer you need a minimum 1gig of ram. I would recommend 2gigs.

As housecat suggested turning off online drc will help speed things up.

The video card is really important once you start working with thousands of pins. Get and Nvidia or ATI card that costs at least $150-200 and you should be fine. Don't forget to turn on direct x.

You can watch a video of the Altium Designer hardware graphics engine here:

**broken link removed**
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
.legend altium gerber

Just to add a little to difflvl's excellent answer - HASL stands for Hot Air Solder Level. It is the same as you are calling a tin-lead finish. They tin the board with solder then blow the excess solder off with hot air to give a smooth finished surface.

As difflvl points out, Europe has gone to lead free solder for all but a few approved critical application exceptions (such as aerospace and defense). When you talk about "tinning" a board with solder these days, you neeed to be careful to specify lead free if your market is governed by the Reduction of Hazardous Substances (RoHS) rules.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
.bad to .pcbdoc designator

thank you both guys!
is plating and finishing the same?
 

altium conductor width

Plating is one of the ways of finishing a board. You can gold plate, silver plate, tin plate, HASL, etc - they are all finishes.

You'll see a lot of abbreviations for the various types of board finishing that can be done - i.e. ENIG (electroless nickle immersion gold), DIG (direct immersion gold), IAg (immersion silver, ISn (immersion tin), HASL (hot air solder level), etc.
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
altium designer relative grid

1- Is AD able to generate netlist for Allegro and PADS?
2- Is AD able to combine two different PCB file? We may want to do this for cutting the project setup cost!
 

why does annotating in altium change schematics?

1. AD can generate a netlist for PADS, but cannot generate a netlist for Allegro. You can see and download the available netlist generators at: https://www.altium.com/community/support/downloads/outputgeneratorsaltiumdesigner6/

2. I'm not sure what you mean by combine two different PCB files. If you mean can AD generate a panel for fabrication - the answer is yes. There are two ways it can be done.

The first method is to use "Embedded Board Array" which is available in the PCB Editor. You create a new board, and embed each of the individual boards into it. "Embedded Board Array" is in the "Place" menu, and there is help documentation that explains how to use it. Both boards have to have exactly the same stackup and number of layers in order to make an embedded board array.

The second method is to panelize in CAMTASTIC. Again, both boards must have the same stackup and number of layers. There is a help document that discusses panelizing in CAMTASTIC.

If your question is about making one board out of two boards. That can be done with copy and paste. An entire board can be copied and pasted, or special pasted, into any other PCBDOC file. If you plan to use integrated functions, you will need to make sure your schematic properly reflects the merged boards. It would probably require resetting and matching unique identifiers for the merged board.

If you mean
 

    Johnson

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top