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interview questions help!

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eexuke

eexuke

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Dear all,
I met with these interview questions, would you mind help me to answer them? Thanks!
1) What is meant by the term "porosity"? Why is it desirable for a cell or macro to have high porosity?
2) What is an "application-specific memory"? What are some specific examples of this part type?
3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?
 

porosity comes form 'porous'. Its basically air gaps in dilectric layers, which reduces the di-electric constant of the layer.

4 or less inputs in a gate: has to do with its input loading. If the input loading is higher, the propagation delay will be high. May be 4 is the sweet spot, and if more inputs are required, then you'd use 2 gates in parallel, and or/mux their outputs.
 

No actually the number of inputs depend upon the speed like if the inputs are more than 4 then the speed will be low so number of inputs limits speed or u can say fan in limits speed and fanout limits propagation delay...

This is the answer for 3 question

give me some points if my answer is correct

Bye take care

Added after 10 minutes:

The second answer is any memory which is unique is called asic ...it wil be specific for that particular application and the examples are FPGA and CPLD


Correct me if i am wrong

Bye take care
 

No actually the number of inputs depend upon the speed like if the inputs are more than 4 then the speed will be low so number of inputs limits speed or u can say fan in limits speed and fanout limits propagation delay...
Click to expand...

1. majju433, what is the difference in speed and propagation delay. I reckon these two are the same.

2. If the number of inputs increase, the size of the p-transisor increases very much, and in order to keep the cell height constant, you have to put a limit to number of inputs, or the gate will become very wide.
Also as you increase the number of inputs, the gate becomes a large load due to the number of transisotrs that would have to be driven. So it will cause the driving gate to get slow.
Kr,
Avi
http://www.vlsiip.com
 

the answers to your questions can be referred to CMOS IC Layout by Dan Klein.
 

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