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Use of a Verilog module in VHDL

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tdesigner

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Dear all,
How can I instansiate a verilog module in my VHDL code?
Thanks every one:D.
 

If you are using Xilinx XST, see your "XST User Guide", chapter "Mixed Language Support", section "Instantiating a Verilog Module in a VHDL Design".
 

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    tdesigner

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?Instantiating verilog module in VHDL is like instantiating any other VHDL entity. you have to follow VHDL rules like width/type matching. because VHDL will not expand/truncate and signal unlike verilog.Also verilog module must be compiled in the library before compiling VHDL.In VHDL compilation sequence is important.

you use port map for instantiating a module
Example
module vlgm(a,b,c)

architecture
begin
i1:port map vlgm(a=>vhd_a,b=>vhd_b,c=>vhd_c)

vhd_a vhd_b vhd_c are signals in VHDL architecture.
 

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