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Help in Digital Converter with VHDL

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Alrite.. the files is ard 40mb.. so i split it up... Just join up and u can use it
 

Ok, I can simulate it in ModelSim, and I see the overflow spikes.

I had to edit DownTB.vhd and remove the all references to rfd and rdy, because they aren't valid ports in dds.vhd.

There's a lot of extra stuff in your RAR archives -- ZIP files and temp files. These are the only files required for simulation:
dds.vhd
dds_SINCOS_TABLE_TRIG_ROM.mif
DownConverter.vhd
DownTB.vhd
filter.vhd
filter2.vhd

I'm now looking for the overflow, but I don't know VHDL very well. Stay tuned . . .

UPDATE:

The overflow spikes are caused by the two "0-X" subtractions in DownConverter.vhd. When X is -512, the subtraction results in +512, overflowing your 10-bit signed integer.

The best way to solve that problem is probably to modify the sine ROM so it swings from -511 to +511 instead of from -512 to +511. I inspected the coregen DDS v5.0 mif file, and it looks like Xilinx messed up the arithmetic. It appears to generate a symmetrical sinewave that swings from -512 to +512, and then it clips the positive peak to +511. That's stupid.

Or try searching your coregen library to see if there's another DDS core available for your target FPGA.
 

Hmm, I've search in CoreGen... That's onli DDS Core, there are afew of those shown but it's the same. What about is there any other way of subsituting the 0-X and X-0?

The best way to solve that problem is probably to modify the sine ROM so it swings from -511 to +511 instead of from -512 to +511
Click to expand...
How do u do so?
 

For a quick and dirty experiment, simply edit the mif file and change all the 1000000000 values to 1000000001. Now both the positive and negative peaks will be equally clipped.

You could write a small program (in C or BASIC or some other language) that rewrites the mif file with a better quality sinewave table.
 

Alrite, Thx alot echo47.
I manage to edit the mif file just by using notepads.
I tested out with 122Mhz and its not giving the spikes already, i'm going to try out with range from 124Mhz and below. Will do updates if any... Thx alot.

Added after 11 minutes:

Updates:

Here's the problem, after each DDS generation of the CoreGen, the mif files seems to be affected. And it got change back to the original state with 1000000000.
After which if i change to 1000000001, it works fine. So the problem here is the mif file will be replace with the new one with 1000000000 causing spikes on the waveform. [/b]
 

I'm glad that helped!

Yes, if you regenerate the core, then it overwrites your modified MIF file. I'm guessing that you are regenerating the core to change the frequency. It may be easier for you to generate a variable-frequency DDS, so you can change the frequency from your HDL.

I generally avoid using cores, because they usually cause me to spend more time than if I had designed the thing myself.
 

Yes, i'm changing my frequency by changing the DDS Core.

It may be easier for you to generate a variable-frequency DDS, so you can change the frequency from your HDL.
Click to expand...
But how? Wat about the coding, what should i write within my HDL code?
 

When generating the core, click "programmable" output frequency instead of "fixed" output frequency. Then feed it your frequency (phase increment) value via the DATA port.

Xilinx recommends using the DDS Compiler v2.0 core instead of the obsolete Direct Digital Synthesizer v5.0 core. The DDS Compiler v2.0 core doesn't suffer the clipping problem.
 

I've search around the CoreGen, mine doesnt haf the DDS compiler v2.0. From wat my supervisor says, he said the spikes could be solve. But he did mention about the amplitude of the wave... but i dont know how to lower the amplitude of my wave. Is there any other way to solve this problem other then implementing the DDS compiler v2.0? All the component instantiate from coregen is assigned by my supervisor.
 

The DDS Compiler core appeared about a year ago, so maybe you need to update your ISE.

By changing those MIF values from 1000000000 to 1000000001, you are slightly lowering its amplitude (and unfortunately adding more distortion). You could rewrite the entire MIF file with a clean sinewave at whatever amplitude you need. Or you could multiply the DDS output by a fraction such as 0.99, but that would consume a multiplier and increase quantization error.

Are you really planning to clock the DDS and other stuff at 500 MHz? That seems too fast for a Virtex-4. (I'm guessing you aren't using Virtex-5 because of the old version ISE.)
 

Oh, my ISE is v8.2i. It's a school property, so i do not know on whether the version is outdated already or not.

By changing those MIF values from 1000000000 to 1000000001, you are slightly lowering its amplitude (and unfortunately adding more distortion).
Click to expand...
How does it add to the distortion? After changing, it seems to be alrite. I ran it with 1-2us more, nothing happens.

You could rewrite the entire MIF file with a clean sinewave at whatever amplitude you need.
Click to expand...
I'm not quite sure how to do this part... rewriting as u mean editing? After editing the MIF file, when CoreGen generates the file will be overwritten.

Or you could multiply the DDS output by a fraction such as 0.99, but that would consume a multiplier and increase quantization error.
Click to expand...
Do u mean adding a new multiplier component into the Test bench and fraction the DDS output by 0.99 b4 going into the filter? Then how will it affect the quantization error? Will it affect my output of sine wave, or giving a better sine wave without spikes?

Err, i'm using Virtex-4. Clocking the DDS is at 500MHz, but clking for the Filter is at 250MHz onli. I've checked and seen that there is a Virtex-5 and Virtex-E too. Wats the different between them? Changing from Virtex-4 to Virtex-5 would haf any affection?

Sry for so much question. =(
But Thank alot for your help... Still need lots of help to complete my project within the next few weeks. :D

Updates :
Alrite, I've tried on generating the DDS with 120MHz output frequency, then i check on my waveform, it looks fine, there is no distortion or spike within it. But when i tried one 121-124MHz, there's still spikes. Also, looking into the Mif file, there isnt any change. Looking this is werild aint it? I'm going to try on below 120MHz to see wat kind of results i get.
 

Changing the value to 1000000001 causes distortion because it's flattening the bottom of the sinewave. It's a small amount of distortion, probably invisible on your HDL simulator display, but it may be significant to your project's signal quality.

You could write a small program that tabulates one sinewave cycle, converts it to ASCII ones and zeros, and writes it to the MIF file.

The multiplier technique could reduce the amplitude of the DDS output, but that signal is already quantized to 10 bits. After the multiplication you would need to quantize it again to 10 bits. That adds more unwanted noise.

Have you tried routing your design? I doubt that DDS v5.0 core will go 500 MHz in a Virtex-4.

Virtex-5 is brand new this year. Lots of cool new features, but not dramatically faster than a Virtex-4. Here's a comparison chart:
https://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/overview/v5v4features.htm

Virtex-E is ancient history, about 8 years old.
 

After few testing, Looks like any output frequency lower then 120MHz does not haf the spike comming out from the waveform. But I also manage to test with 130MHz. Onli 1 output waveform is giving the spike. Then with 125MHz, the Frequency output i should get is 0Hz, which has no problem. So i suspect any frequency from DDS generated above 121MHz will produce the spikes.

By the way, do u know wat's the cut-off frequency or cut-off point for the filter? I wan to tally with my 120MHz,70MHz waveform's amplitude. To know whether my filter is working correctly.

I've attach a 130MHz waveform generated. maybe you could take a look at it.
 

Basically, within my design, i will be onli doing on the programming part and simulating out the waveform which will generically suit to my project which is down-converter.. Routing might be passed on to another student who will take over my project.

Added after 7 minutes:

I think adding a multipiler isnt a ideal way . cause like u have said adding multiplier will result in having higher noise..

You could write a small program that tabulates one sinewave cycle, converts it to ASCII ones and zeros, and writes it to the MIF file.
Click to expand...
Is it possible you can gif mi an example? since u haf my programs already, it might be easier for u to do it? cos i'm doing all the programs all base on VHDL onli.

Added after 1 hours 32 minutes:

The Mif file is original. I think u might get the wrong idea. That waveform i've attach is a -10Mhz output wave, using 135MHz sine wave output from DDS core. I set it at the output frequency. It's 125MHz-135Mhz resulting a -10MHz wave form.
Generally, it's like (125MHz-DDS output frequency = Down-converter Output)

I've attach the whole file of my Down-Converter. Using xilinx to open project it could prolly load everything.
 

Is your 135 MHz waveform using the core's original MIF file, or a modified MIF file? You have to modify the MIF file to eliminate the spikes.

I can't reproduce your 135 MHz waveform exactly. Maybe you've changed other things in the system?

As you change the DDS frequency, it picks different points along the sinewave. Some frequencies will hit the bad -512 values, some won't.

I don't know the filter characteristics. I didn't find the corgen project setting file in your first set of RAR archives.

Here's a C program that generates a new sinewave in MIF format:
Code: 
#include <stdio.h>
#include <math.h>

#define N         1024  // sinewave points
#define amplitude 511   // sinewave peak amplitude
#define bits      10    // quantization bits

int main(void)
{
  int n, s, b;

  for (n=0; n<1024; n++)
  {
    s = floor(amplitude * sin(2 * M_PI / N * n) + 0.5);
    for (b=bits-1; b>=0; b--)
      putchar((s >> b) & 1 ? '1' : '0');
    putchar('\n');
  }
  return 0;
}
Here are two program runs. One has amplitude 500, the other has amplitude 511:
 

How should i use this file? If i use this files, the coregen will still overwrites it.
Also is it possible to implement C program into VHDL? else how to i make use of that C program u haf written?
 

Try setting the MIF file to read-only so coregen can't overwrite it.

If you don't have a C compiler, then I guess my little program is useless to you, except as documentation showing how I created the reduced amplitude MIF files. I don't know if it can be translated into VHDL. That seems like a strange idea -- is VHDL the only compiler you have on your computer?
 

Oh... nop.. there's many other programs... just that my project is purely base on VHDL onli. Because i dont haf any hardware to program for my project too. I'm doing purely on VHDL basis. My title is Developement of Down-converter for SDR system. The given program to do is onli VHDL.

Alrite. Setting the Mif file to read onli then how can i set it that my program will use that Mif file rather then the one that is generated from Coregen?

Updates :

Hmm... From wat u haf said. I went back to the dirty method on changing the '1000000000' to '1000000001' for the Mif file and set it as Read-Only file. Making the CoreGen not to over writes the Mif file. =D
But do u think this is a good method? Will it affect my testing in future?[/b]
 

Ok, VHDL only. But it's very common to use a variety of math and programming tools to create pieces of an HDL project. You are using coregen to create most of the code, and it's a big clumsy Java application.

You can rename my MIF file to dds_SINCOS_TABLE_TRIG_ROM.mif so the core will find it. Or look inside dds.vhd and you'll see where it loads the file name.

These are all clumsy workarounds to fix an inadequate or broken core. It's yet another example of why I generally avoid using cores.

By the way, Xilinx tells me they know the DDS v5.0 core is broken, but they no longer support it.
 

Oh i see... that's quite bad. But i've just set the Mif file to read-only, making the COREGen not able to overwrite the mif file. Then i tested out with most of the frequency, the outcome of the waveform is good. It seems that there is no more spikes showing up. A very Big Thanks for this.

I'm just wondering how could you make the DDS without using the core? I've see the Vhdl code for DDS which is way too long.

Now, here's a lil' problem. How to determined the cut-off frequency for the DA FIR filter. There's a graph shown for magnitude against the normalised frequency from the COREGen parameter there.
 

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