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Question for a bias circuit

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fengluan

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For the following circuit:
91_1184579135.gif


if Vdd=Vdc=5V ,the current is ok
if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated.

why for this ?
and how can i eliminate osc.

The start circuit i added has no effect for this .

thanks .
 

fengluan said:
For the following circuit:
91_1184579135.gif


if Vdd=Vdc=5V ,the current is ok
if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated.

why for this ?
and how can i eliminate osc.

The start circuit i added has no effect for this .

thanks .
Click to expand...

hi
increase the resistor value or decrease the size ratio of two nmos transistors may do work, i think.
good luck
jeff
 

The circuit is unstable. It may need a compensation capacitor
 

This circuit is a positive circuit if you analyze it carefully, so in order to make it not oscillating, you have to make the loop gain less than one.
 

thanks

I have simulated it ,the loop gain is -5dB, but it's still oscillate.
But when decrease Width of two pmos ,then no osc.

i confused for it .
 

Nmos 12u/3u m=2
m=16
Pmos 20u/3u m=2

R: 50k
 

Try add two capacitors at the gates of pmos and nmos.
 

You may try ac analysys and get the PM.
 

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