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16 bit Upcounter in VHDL (ISE 4.2 )

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kollosse

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Hi,

how can i progammed a 16bit upcounter under VHDL.

I use ISE 4.2 and a XC9572XL PLCC44 CPLD (XILINX)

How must i assing the Counter-outputs [D15..D0] to the pins.

Sorry but my english is not so good.

Johann
 

reading your email I understand that you are a newbie to VHDL and FPGA/CPLD design, is that right?

In that case you need some basis before you fry a chip. I would suggest you to have a look to some tutorials (search in this group) of VHDL and FPGA/CPLD design.

Basic steps :roll: :

1) write your VHDL for the counter
2) simulate it
3) synthesize it
4) P&R it, for this you need to map it first using a UCF (User Constraint File), this file is where you write the LOC (location) of your pins, where your internal signals are connected.

Good luck,
- maestor
 

I believe that maestor is right
if foundation ISE you can find examples that contain VHDL code for counter. and the quick manual accessed from the help had quick guid that explain pin assignment

regards
 

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