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About inout ports in verilog

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int19

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verilog inout

Hi!
I'm unfamiliar with verilog so this is my simple question.
my netlist has some inout ports that must function as in ports (but i can't change them) so i've to add a tristate buffer. My code is similar to this:

module top(a,b,c,enable)
input enable;
inout a;
inout b;
output c;

if (enable=='0') begin
a<='Z'
b<='Z'

end
end module

I get this error on ncsim: a net is not a legal lvalue in this context [9.3.1(IEEE)]
I also tried assign and = but it didn't work.
What's wrong?
Thanks.
 

inout verilog

inout are actually "wire" so you can't use any procedural assignments. You need to use continous assignments.

inout a,b;
input wire enable;

wire a_out, b_out;
wire a_in, b_in;

//output assignment of inout port
assign a = (enable) ? a_out : 1'bz;
assign b = (enable) ? b_out : 1'bz;

//input assignment of inout port
assign a_in = (enable) ? a : 1'bz;
assign b_in = (enable) ? b : 1'bz;
 

verilog inout reg

i studied that u can ue inout for reg also but how to use it
 

inout in verilog

hi !
I guess u'll face synthesis problems if u use inout in always block . what u do is u create a temp reg and assign the inout value to it using continuos assignment statement and now u can use the temp reg value in the always block

pls correct me if i am wrong

thanks and regards
Deepak
 

inout port in verilog

thanks for the help.
I've resolved this problem in a similar way, defining a "mask" which instantiate the module and with an enable IN port and the same INOUT ports of the module.
This way doesn't work with a vhdl mask and a vhdl module, but works fine with vhdl mask and verilog module! It's curiously true...

Thanks again.
 

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