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  1. S

    corner sim in ADE---pcf file and library problems!!! urgent!

    corner simulation ade Hi, dear all, the above problem has be settled by myself. In the corner analyse, there shouldn't be "." or "-"in the corner name, otherwise, there would be strange interruption like "remote calling". Please pay attention to it.
  2. S

    corner sim in ADE---pcf file and library problems!!! urgent!

    pcf file Dear all, I am trying to do some corner simulation in the ADE of candence, using the tool->corner... I use the tsmc018 process. I wrote a model file as cor_p3_libs.scs (following): library cor_p3_libs section tt_1.8_27 include "../rf018.scs" section=tt include "../rf018.scs"...
  3. S

    anyone know bandwidth function in cadence? it seemed wrong!

    Re: anyone know bandwidth function in cadence? it seemed wro Hi, dear all, the following is the answer I got from an AE in cadence, hope it would be helpful. For your first question, you can ignore 20dB for your output because 20dB is included in bandwidth function. For example, if you want...
  4. S

    anyone know bandwidth function in cadence? it seemed wrong!

    Re: anyone know bandwidth function in cadence? it seemed wro Thank you for your kindness, but maybe I didn't clearify it. I use the new versions of calculator ---wavescane here. And the bandwidth function is directly listed in it. I use 20dB(Vf (outp)-Vf(outn)) to get the gain. And then, I use...
  5. S

    anyone know bandwidth function in cadence? it seemed wrong!

    Hi, dear all. Are there anyone familiar with the wavescan calculator of cadence? It seemed to be totally wrong. I use it to measure the 3dB bandwidth, whether it is low, high or band, the results go far from the right values. Are there any settings that I should be careful of? Or is it just a...
  6. S

    help needed on the standard of the supply voltage of IC

    So, what about the 0.5um? Then, if it is a 0.18um process, whether it comes from TSMC or UMC or other factories, the supply voltage would be 3.3V, right? Do you mean that it is a sticked standard? So, what is this standard? Would you please give me some more suggestion?
  7. S

    help needed on the standard of the supply voltage of IC

    0.18um supply voltage Dear all, I am now confused by the supply voltage of IC. It seems to be related to the process. For example, the TSMC 0.18um tends to use both 3.3V and 1.8V, and 0.25um process tends to use 2.5V, while 0.6um or so use 5V. But, why it is 5V rather than 4.5V, why it is 3.3V...
  8. S

    help on the theoretical backgroud of RSSI

    Thank you very much. I have this materail. But, what I am wondering is, the theoretical explanation of RSSI. Why piece-wise approximation can approximate Logrithmic funcion? And the other method? What is the function behind them? Like the taylor function ln(1+x)=1+X+....? Could any one...
  9. S

    help on the theoretical backgroud of RSSI

    Hi, friends. I am doubting on the theoretical background of RSSI. There is majorly 2 may to get the logrithmic function for RSSI. First is the piece-wise approximation, used in cascaded amplifiers. Second, which I am not so sure yet, is dependent on the direct power detector which is composed of...
  10. S

    can active inductor be used with source follower?

    Hi, dear all. I am desiging a cascaded CMOS amplifier with broadband and high gain. One soluion to get broad bandwidth is the use of active inducto formed by NMOS and Resistor. My qustion is , in the papers I read, I found that where the activce inductor is used, no soure follower is followed...
  11. S

    choice between LA and AGC

    Hi, friend. I know that LA(limiting amplifier) and AGC( automatic gain control) are 2 candidate for the post amplifier/or Main amplifier in optical tranceiver. And I already know some of their advantages and shortcomings. I have 2 quesions: (1) Since LA is more fast in transient response(no...
  12. S

    the definition of sub-threshold area

    Hi, friends. I know that when Vgs get very close to Vth, the operation area is called sub-threshold area. But, is there a clear definition, a water shed on it? I mean, judge by the value of Vth and Vgs. In the *.lis file produced by hspice, the states are only divided into saturati, cutoff and...
  13. S

    negative CMOS capaticance

    cgd cancellation inductor Hello, friends, thank you all for your clear answers. I did the simulation as tsb_nph suggested. And here is the answer: The gain of each stage is about 15DB, and it remain unchanged. The value of Cgd is about 10ff, and here is the simulation result of single...
  14. S

    negative CMOS capaticance

    phase shift right hand plane zero Hello, friends. I've just tried the method aryajur suggested. I added a capacitance of about 200ff to the gate of each stage of differential amplifiers to decrease the total 3dB bandwidht from 642MHz to 554MHz. Then, I added the crossing MOS CAP again, the...
  15. S

    negative CMOS capaticance

    avoid miller capacitance in differential pair Hi, friends, thank you all for your clear answers and patience. As for what I said about positive connected MOS CAP and negative connected MOS CAP, I will attach a graph here to illustrate it more clear. In my opinion, the diffecent cap between...
  16. S

    negative CMOS capaticance

    capaticance Dear Vamsi Mocherla, the negtive MOS capacitance is realized in this way in the attached file1. In fact, it is formed by negtive miller capacitance. And I use MOS cap here to replace the normal cap. Like what a paper used in attached file2. To my disappointment, it doesn't...
  17. S

    negative CMOS capaticance

    cmos negative capacitance Dear all, I am trying to get 2 negative capacitances used in differential pairs to enlarge its bandwidth. I use the gate of a NMOS transistor as the "positive" end and, connect the drain and source of it as the "negative" end. I found 2 strange things.:cry...
  18. S

    doubt on simulating the startup circuit

    Thank you all again:D. With all your answers, I went on investigate into this issue, and got a new question. As electronranher said, slower ramps are always worst case, but I found that, without the startup circuit, if I increase the end point of transisent simulation, the circuit would...
  19. S

    doubt on simulating the startup circuit

    Thank you all for your clear answers. But the startup circuit for bandgap differs a lot from its conterpart in self-biased current source, right? And, I've found in other related topics in this forum that DC analysis is also needed. Why DC analysis is needed here? I try to sweep the VDD from 0...
  20. S

    doubt on simulating the startup circuit

    Thank you, leichen_gy, thank you for your experience. But, I feel even more puzzled now than before. :cry: If your bandgap may not start with startup circuit, then, what I can do to know if the circuits, like self-biased current source will startup by simulation? And what's the meaning of...

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