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  1. ravics

    numerically controlled oscillator (for SDR) in FPGA

    What equations are you referring to?
  2. ravics

    Xilinx DSP slice Comparison

    Link below has a comparison table in the end. I hope it answers your question. https://fpgaconcepts.wordpress.com/2012/05/29/dsp48/
  3. ravics

    numerically controlled oscillator (for SDR) in FPGA

    You may use DDS IP Core provided by FPGA Vendor.
  4. ravics

    digital signal processing with FPGA

    Start with Matlab/Simulink. FPGA's have a lot of IP cores to implement DSP functions. You could also have a look at System Generator.
  5. ravics

    Resample in Xilinx System Generator?

    You may need to do a combination of interpolation and decimation using cascaded CIC filters or FIR filter as mentioned in previous post.
  6. ravics

    [SOLVED] CIC Decimation output - Phase

    Thanks. FIR filter with Linear Phase is usually stated explicitly but didn't hear the same about CIC filter output. That's why had a doubt. A google search reveals that CIC filters are a class of FIR filters.
  7. ravics

    [SOLVED] CIC Decimation output - Phase

    I'm using Xilinx CIC Compiler IP. Does it cause phase change in the output?
  8. ravics

    [SOLVED] Amplitude Variations in SSB Demodulated Output

    It was due to mismatch in clock phase. I hope this helps others.
  9. ravics

    FPGA Real to Complex Conversion

    thanks @TrickyDicky
  10. ravics

    FPGA Real to Complex Conversion

    How can I convert real-imaginary to complex signal using Xilinx FPGA IP cores?
  11. ravics

    Suggest books for beginners in FPGA

    Re: Suggest books for FPGA I've listed Must Have FPGA Bookmarks on my blog. You can find it here.
  12. ravics

    FPGA beginner needs links to tutorials - experienced people help please !

    I've compiled a list of interesting FPGA links in my blog - have a look at fpga-blog.tumblr.com/links
  13. ravics

    Software Defined Radio Implementation on FPGA guidance

    Have you gone through USRP? If not just google "USRP" - it may be a good starting point.
  14. ravics

    LCD interfacing with FPGA using SPI

    You need to follow the initialization sequence for your LCD interface. Timing has to be followed according to datasheet's timing diagram for LCD Enable, Register Select, Read Write & Data bits. You may use a state machine running on SPI clock. After initialization sequence data can be sent to...
  15. ravics

    VLSI career in Bangalore & Schools on VLSI

    C-DAC is alright but broad in scope & content.
  16. ravics

    Flash Memory access in microblaze

    Did you try adding Flash_EMC peripheral?
  17. ravics

    [SOLVED] Configuration problem in ml605

    Have you checked configuration modes of multi-purpose select DIP Switch S2? You need to adjust the mode pins in BPI mode. Check UG534.
  18. ravics

    How Can I Build a Digital Clock Manager In VHDL

    Seems to be a complex task. Clock dividers are easy to code in VHDL/Verilog.
  19. ravics

    Multiply two signals in VHDL with FPGA output

    You could use Multiplier IP Core as you're using Xilinx SP601.

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