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  1. ravics

    [SOLVED] CIC Decimation output - Phase

    I'm using Xilinx CIC Compiler IP. Does it cause phase change in the output?
  2. ravics

    FPGA Real to Complex Conversion

    How can I convert real-imaginary to complex signal using Xilinx FPGA IP cores?
  3. ravics

    Edge detection using Combinatorial Logic

    Is there a way to design an edge detection digital circuit without using Sequential logic?
  4. ravics

    [SOLVED] Amplitude Variations in SSB Demodulated Output

    I've used Weaver's SSB Demodulator method. Though the frequency of demodulated signal is perfect, there are amplitude variations in the envelope of the signal. I'm using FPGA to implement the demodulator. What could be the problem for amplitude variations in the demodulated signal?
  5. ravics

    [SOLVED] Chipscope Multirate Outputs Debug

    Can we have two clocks for trigger signals to be monitored on Chipscope? What is the way to monitor multirate data with chipscope? I have a design with an output signal with high decimation (>1000). I want to monitor both the high sample rate signal as well as the decimated signal. Is there...
  6. ravics

    [SOLVED] SLV into System Generator Block

    How can I input std_logic_vector into system generator blocks? Constant block supports fixed, boolean & dsp instructions. Is there any way to force slv as input to another sysgen blk?
  7. ravics

    Xilinx FIR Compiler IP

    What is the fomula for calculating Passband & Stop band in Filter Analysis Window of Xilinx FIR Compiler? It shows Passband & stop band values normalized between 0 & 1. What are optimal values?
  8. ravics

    CFIR filters - Xilinx IP Core

    How can Compensation FIR filter be implemented using FIR Compiler IP in Xilinx FPGA? Any reference designs?
  9. ravics

    Hardware Co-simulation with Avnet V4 Memec Board

    Need System Generator reference design/tutorial for Avnet Virtex-4 Memec Board. I'm facing problems with JTAG Co-simulation & Generation.
  10. ravics

    Automatic Gain Control - Audio AGC in FPGA

    How to implement Audio AGC in FPGA using VHDL? Any IP cores available? Input is 16-bit,8 kHz demodulated audio.
  11. ravics

    Adding noise to Test Sinusoid

    I have generated pseudo random number using LFSR to use it as AWGN. How can I add awgn to a test sinusoid. How can I change the SNR (in dB)? My sine is 16-bit & PRNG is also a 16-bit value.
  12. ravics

    Features in latest VHDL

    What are the best features in the latest version of VHDL? Is VHDL-2008 the latest? Any link to the list of latest features with examples?
  13. ravics

    Logic Vector Division using SRL

    Can we divide an std_logic_vector using 'SRL'? I need to divide a logic vector by a power of 2. What is the syntax?
  14. ravics

    VHDL 2008 - ALL in Process Sensitivity List

    I've come across keyword ALL to use in VHDL sensitivity list similar to * in verilog. I believe its added in VHDL-2008 features. However, when I use it, compiler throws an HDL Parsing error. Do I need to add any specific libraries to compile with Xilinx ISE native HDL Compiler?
  15. ravics

    Reload Design in Modelsim (Xilinx ISE + ModelSim)

    1. Is there a way to reload the VHDL design in Modelsim without going back to ISE by using scripting commands in modelsim? 2. What is the procedure to compile UNISIM & Xilinx Corelib in Modelsim? I got this note from one of the university tutorials : Restarting and running the simulation...
  16. ravics

    Spectral Averaging VHDL

    How can I perform spectral averaging using VHDL? I'm getting output from Xilinx FFT IP Core & need to average several successive spectra? What is the methodology? Any sample code of averaging for efficient synthesis?
  17. ravics

    Standard IF 455k, 10.7M, 70M

    Why are 455kHz, 10.7MHz, and 70MHz most widely used standard IFs? Is there any particular reason for chosing these specific frequencies?
  18. ravics

    Simulation of PowerPC on Xilinx FPGA

    Is there a way to simulate the PowerPC on Xilinx FX FPGA using HDL Simulation in EDK? I want to test the functionality of PowerPC without having the board. Any other simulation tools available to simulate powerpc?
  19. ravics

    PowerPC on Xilinx FPGA

    Are there any good tutorials available for PowerPC based designs on Xilinx FX FPGAs? Any suggestions for low end board with FX series FPGA?
  20. ravics

    Synthesizable Operators in VHDL

    Which of the following operators are NOT synthesizable by Synthesis tools? * + - &

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