Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I've used Weaver's SSB Demodulator method. Though the frequency of demodulated signal is perfect, there are amplitude variations in the envelope of the signal. I'm using FPGA to implement the demodulator.
What could be the problem for amplitude variations in the demodulated signal?
Can we have two clocks for trigger signals to be monitored on Chipscope?
What is the way to monitor multirate data with chipscope? I have a design with an output signal with high decimation (>1000). I want to monitor both the high sample rate signal as well as the decimated signal. Is there...
I've come across keyword ALL to use in VHDL sensitivity list similar to * in verilog. I believe its added in VHDL-2008 features. However, when I use it, compiler throws an HDL Parsing error. Do I need to add any specific libraries to compile with Xilinx ISE native HDL Compiler?
1. Is there a way to reload the VHDL design in Modelsim without going back to ISE by using scripting commands in modelsim?
2. What is the procedure to compile UNISIM & Xilinx Corelib in Modelsim?
I got this note from one of the university tutorials : Restarting and running the simulation...
How can I perform spectral averaging using VHDL? I'm getting output from Xilinx FFT IP Core & need to average several successive spectra?
What is the methodology? Any sample code of averaging for efficient synthesis?
Is there a way to simulate the PowerPC on Xilinx FX FPGA using HDL Simulation in EDK?
I want to test the functionality of PowerPC without having the board. Any other simulation tools available to simulate powerpc?