Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. dianin

    Reason why my Scan-simulation is failing with post-layout netlist?

    Hello Friends, My scan-simulation is failing with post-layout netlist with SDF annotation. I'm seeing some timing violations in log file. Could anybody suggest how to debug it. Also the post-layout STA was clean (e.g. no setup/hold violations in scan-mode), then why during simulation I'm...
  2. dianin

    Very Low transition fault coverage, please help

    I'm getting very low transition fault coverage (56%). The tool is cadence's Encounter Test which is pretty new to me. Could anybody suggest how to debug it. What could be the cause of low coverage. The stuck-at fault coverage is around 97%.
  3. dianin

    How to generate transition fault in encounter test?

    Hello Friends, I'm new in Encounter Test(cadence tool for ATPG). I want to generate transition fault. I came to know that need to insert the OPCG (On Product Clock Generation) logic during synthesis for this. Is any other way to generate the transition fault without inserting the OPCG, if yes...
  4. dianin

    Recommended books on computer memories

    Could anybody suugests the good books on computer memories (volatile and non-volatile). I'm looking for a book which have the detail of operation, function and usage of all kind of memories. Thanks
  5. dianin

    Getting 0 FSM extraction , PLEASE HELP

    Hi All, I'm using Cadence's Incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file ...
  6. dianin

    Flow for metal mask functional ECO

    I want to do metal mask ECO. There are some changes in RTL , I do not want to resynthesis and PnR instead map the new logic using only the spare cells. Could anybody share what is right way of doing this both at synthesis and layout stage? Is there any automated way ?
  7. dianin

    IC Compiler : Scan reordering vs CTS in scan-mode in MCMM

    To optimize the scan-path (usually the hold violations in scan mode), we either do scan-reordering or CTS in scan-mode in MCMM flow. Could anybody explain which way is more beneficial and why. In scan-reordering , during placement it reduce the scan-chain length to avoid the congetion but...
  8. dianin

    communication skill vs technical skill

    Hello All, Does better communication really attract others, even if you have very little technical knowledge. I am writing this post, as from couple of years I experienced that hardwork and having good technical knowledge do not help to get attention from your seniors and not even consider for...
  9. dianin

    Low power in scan mode

    Could anybody explain why low-power is important in scan-mode and what are the techniques can be used? Any inputs is highly appriciate.
  10. dianin

    Suggest books for verification of AMBA based system

    Hello Friends, I'm new in microcontroller. I want to learn AMBA based system verification ,specially the programming. Could anybody suggest books or document for begginers for the verification of AMBA based system?:-? Thanks
  11. dianin

    How to get cascaded clocks information at synthesis level

    Can anybody tells how to get cascaded clock information at the synthesis level? Cascaded clocks are the master clocks which are defined at the fanout of another master clock. For example design have two clocks one is CLK1 at top-level and CLK2 which is defined at hierarchical level but is the...
  12. dianin

    Encryption of TCL script

    Can anyone suggest how to encrypt the TCL script, it should not be readable but can be used correctly in digital tools like Design compiler, IC Compiler. Thanks
  13. dianin

    [SOLVED] Tutorial for DFT and ATPG

    Could anyone provide the tutorial for DFT and ATPG? Thanks
  14. dianin

    Connet AHB-lite bus master to full AHB system

    Hello Friends, What are things need to be taken care when connecting the AHB lite bus master to full AHB system? Thanks, Dianin

Part and Inventory Search

Top