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My scan-simulation is failing with post-layout netlist with SDF annotation. I'm seeing some timing violations in log file. Could anybody suggest how to debug it.
Also the post-layout STA was clean (e.g. no setup/hold violations in scan-mode), then why during simulation I'm...
I'm getting very low transition fault coverage (56%). The tool is cadence's Encounter Test which is pretty new to me. Could anybody suggest how to debug it. What could be the cause of low coverage. The stuck-at fault coverage is around 97%.
I'm new in Encounter Test(cadence tool for ATPG). I want to generate transition fault. I came to know that need to insert the OPCG (On Product Clock Generation) logic during synthesis for this.
Is any other way to generate the transition fault without inserting the OPCG, if yes...
I'm using Cadence's Incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file ...
I want to do metal mask ECO. There are some changes in RTL , I do not want to resynthesis and PnR instead map the new logic using only the spare cells.
Could anybody share what is right way of doing this both at synthesis and layout stage? Is there any automated way ?
To optimize the scan-path (usually the hold violations in scan mode), we either do scan-reordering or CTS in scan-mode in MCMM flow. Could anybody explain which way is more beneficial and why.
In scan-reordering , during placement it reduce the scan-chain length to avoid the congetion but...
Does better communication really attract others, even if you have very little technical knowledge. I am writing this post, as from couple of years I experienced that hardwork and having good technical knowledge do not help to get attention from your seniors and not even consider for...
I'm new in microcontroller. I want to learn AMBA based system verification ,specially the programming.
Could anybody suggest books or document for begginers for the verification of AMBA based system?:-?
Can anybody tells how to get cascaded clock information at the synthesis level?
Cascaded clocks are the master clocks which are defined at the fanout of another master clock. For example design have two clocks one is CLK1 at top-level and CLK2 which is defined at hierarchical level but is the...