Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. R

    [SOLVED] DC offset remova and phase issues

    Re: DC offset removal and phase issues Ah yes, more bits. I suppose I should have tried that earlier. I was going between 8 and 12 and didn't notice much of a difference but 20 seems to fix it. Thanks.
  2. R

    [SOLVED] DC offset remova and phase issues

    DC offset removal and phase issues The current filter I use is from the Xilinx app note on dc offset removal. However, it adds a noticeable phase shift to my signal of 9 degrees at the highest frequency, and around 40 degrees at the lowest. I am comparing this signal with a square wave and the...
  3. R

    Displaying code in multiple languages

    Yea, I can add an identifier, shouldn't be too bad. As far as adding and subtracting messages, I do not plan on letting it be run-time configurable. It should be all set up before hand and all that happens at run-time is the mapping of the messages in the selected language to the message array...
  4. R

    Displaying code in multiple languages

    I have an SD card hooked up through SPI, which is like 1 GB. I figured I could store text files, one per a language, that has all the text blocks per a line, in the SD card. This is as far as I got. I was thinking then, I would have the text blocks mapped to specific locations in memory. Each...
  5. R

    Displaying code in multiple languages

    I've never had to do this before and I'm having troubles finding some good references on this topic. What I have is an embedded system with a GUI that is displayed in English. What I want to do is allow for the user to go into settings and pick their language of choice from a list and then have...
  6. R

    Multiple input PID loops

    Yes, this is exactly what I was thinking I had to do, which I mentioned in my first post. I just wasn't sure if it was a band-aid fix or a reliable one.
  7. R

    Multiple input PID loops

    The system is a parallel resonant LC with a coil on the output. The coil changes with the application. Big coil for bigger loads, small coil for smaller load. The inverters output goes to a transformer and then goes to the output coil producing eddy currents which heat the metal in the coil. The...
  8. R

    Multiple input PID loops

    The system varies as the output load is metal. As the power put into it heats it up its properties will change causing the Q curve to shift and change. Some metals, as the go into curie, cause the systems parameters to rise extremely fast. Normally, I would just control power and then cascade it...
  9. R

    Multiple input PID loops

    I'm controlling the frequency of the MOSFETS on an inverter, which goes to an LC tank. The current(RMS) limit is for the specs of the MOSFETS. The voltage (RMS) limit is for the limit on the caps on the tank. The phase limit is to prevent the system from operating below resonance. The power...
  10. R

    Multiple input PID loops

    Multiple SISO PID loops I have a system that I'm trying to control using feedback that receives voltage(rms), current(rms), phase, and line input power. Currently, I put all these signals into separate PID loops and then take the smallest value of the outputs. This works fine in the steady...
  11. R

    Phase error calculation of current transformer

    Hey, I am trying to understand how to model the phase error of the current transformer I'm using in my project. It is a triad cst206-3A with a 1:300 turn ratio, ET of 6000 v/uSec, min inductance of 130 mH, a max DCR of 12.4 ohms, and primary amps of 70 RMS. There is also a burden resistor of 22...
  12. R

    Problem with input signals in ADC quantization

    Re: ADC quantization Yes, that EVM. Yea somewhat, I used a bunch of signals started with -1V to 1V and I still got the same results so figured there was no DC coupling. But, I got confused when looking in other threads how they determined their quantization factors and the data sheet listing...
  13. R

    Problem with input signals in ADC quantization

    I'm using the eval kit TI ADS62P22, 12 bit 65 MSPS. I'm running it off the internal reference common mode which is listed as 1.5 V and a REFT as 2 and a REFB as 1. The problem I have is I don't understand the numbers I get from the input signal. They look like the input signals in shape and...
  14. R

    Signal integrity for ADC (LC filter question)

    Looking at the signal 100KHz from the generator into the oscilloscope I can see a variance of 30mV over 30 ns where the signal is spiking.
  15. R

    Signal integrity for ADC (LC filter question)

    No I haven't done any FFT yet I'm pretty new to this. Basically, I'm just trying to evaluate the accuracy of the ADC using a sine wave and find out what its limitations are. The ADC is a TI ADS62P22. The important question I guess I have is, is this a signal integrity problem or is the range...
  16. R

    Signal integrity for ADC (LC filter question)

    I have an ADC that samples 12-bits at 65 MHz that I'm feeding into an FPGA. At the moment, I'm just trying to evaluate the ADC. It has a typical SNR of 71.6 dBFs, a SINAD of 71.5 dBFs, THD of 93dbc. When I put a low frequency sinusoidal signal from a HP 33120A signal generator at around 100kHz I...
  17. R

    Problem with VHDL code for subtraction

    Re: Need some VHDL help Well more or less I can figure out the zero crossings without any false crossings. This means if the waveform changed frequency I would only find out on the zero crossings which at 100KHz could be roughly 5 us. Now, I'm trying to figure out if I can figure out a change...
  18. R

    Problem with VHDL code for subtraction

    Re: Need some VHDL help Yea that works but I was looking for something that would know in real time, not at the end of the half period. It seems to me at least, that the range at 100kHz provides such a small slope change that being able to distinguish the actual peak value is impossible without...
  19. R

    Problem with VHDL code for subtraction

    Re: Need some VHDL help It ended up being the clock issue. I had the wrong clock connected to the component. Instead of using the clock coming back from the ADC I was using the clock going to the ADC. So, I was getting wrong values registered in. Anyways, put in a register on the input and now...
  20. R

    Problem with VHDL code for subtraction

    Re: Need some VHDL help The subtraction is not giving me the correct result when I'm looking in the signal tap results. For example, it lists current at 18, prev_current at 37 and the subtraction result of 4. This is incorrect. Basically I'm trying to write some code to find some extremes and...

Part and Inventory Search

Top