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Well, thank you very much for your suggestion. But, there is some problem.
I avoid using delayer here since it will bring trouble. So, I will try to use the DIS signal itself as the clock of the RS trigger. Attention that the DIS is not a periodical signal. Thank you very much!
Hi, friends. I encountered a problem. There is a logic sigal DIS which will become an impulse by random. I wanna distill it's falling edge when this change occurs. Here, I used RS triggers. (I built them by nmos and pmos and simulated with hspice.)__master-slave RS trigger built on NAND gates...