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What I've implemented is at https://github.com/w-tr/digital_filters/tree/master/lowpass/rtl
From my understanding, #7, wouldn't it be better to have -raw signal -> deglitch -> debounce (basically the otherway round?)
Behind the EU restrictive GDPR legislation which is why a lot of companies dont' bother servicing this dying Union.
So I can't see this https://www.hamsters.io/
However if you want the guys github try
He's been active in July2020, so you could ping him a...
I'm trying to understand the difference between a deglitch and debounce circuit. I saw something here, but I've never seen a debounce that doesn't reset count on a change...seems like what sh1 was implying is a debounce is a moving average.
Maybe someone here can help me with the...
TrickeyDicky you should write a book.
I hadn't noticed that he was selectively directing a function, in addition to the types. I'm so used to seeing an infix function used as a (func) b, that I completely forgot the written implementation is "func" (a : type, b : type). However...
Background - After 10 years in the business I was writing my own collaborations of VHDL rules/ best practices etc. I decided to review one of the books on my shelf, "The student Guide to VHDL" by Peter J. Ashenden.
Chapter 7.1 Package Declarations, Figure 7-1 and Figure 7.2
Well in my design. IT works for synthesis. However I didn't use xsim for simulation because it couldn't handle vhdl2008.
if rst then
killed the xsim. It just cannot handle inferred (??) operator. Therefore I'm not surprised if it cannot handle pragma commands. Give RTL_SYNTHESIS...
What I've discovered -
Easiest solution to overcome my problem on a Xilinx device is to instantiate a xpm block - xpm_cdc_single/xpm_cdc_array_single.
However when trying to be clever/unnecessarily complex. I've looked at
a_scoped_xdc file and
Situation is a follows.
Design in Vivado 2018.4
Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals. Furthermore I've created an entity that structurally instantiates the collection of sync'ing FF required to...
I was aware that the ^ - equivalent to "cd .." - looks up a level.
However I'm surprised to see that the order of block declarations matter. Although the statements declared within the architecture are concurrent to each other, it appears that the order matters. I don't know...
This following is a derived from my desire to keep a signal declaration local to a specific block, but use it in a different block. I know if I was to move the "scope" of the signal declaration to the architecture I would be able to apply visibility by selection.
Can a signal local...
if rising_edge(clk) then
prev_read_addr <= read_addr;
if rising_edge(clk) then
if prev_read_addr /= read_addr then
r_valid_slv(0) <= '1';
elsif we='1' then
r_valid_slv(0) <= '1';
r_valid_slv(0) <= '0'...
How important is portability vs vendor ip instantiation?
Just a brain dump - Based on the code presented you'll always have to wait 1 cycle after we='1' before your see write value pushed out onto the read q signal. Why not assign a valid signal associated with your read that is either delayed...
I want to help, but this is blatant offloading of work. How are you going to get any better?
You need to know the following
1. You use the clock to generate a counter.
2. Based on clock speed a certain multiple will give you a second.
3. You can represent events that tick over to implement...
Step 1, create a vector-array of your data
Step 2, Use generate statements to iteratively connect the previous.
type x is array<> of std_logic_vector(<>)
signal data_in : x ... -- note this is pseudo code.
G_label : for I in array_range generate --loop
uut : component...
Step1 Make sure you're not using any form of AES like CipherBlockChaining (at least not until you know where you are in the chain)
Step2 Framing the data as outlined by #3 is a good place to start.
Sweet. I found it useful for generating a ramp (counter), however interestingly it has no affect on the signal value.
wave create -pattern counter -startvalue 00000000 -endvalue 11111111 -type Range -direction Up -period 50ns -step 10 -repeat 5 -range 7 0 -starttime 0us -endtime...
My version of modelsim/questasim doesn't even have create_wave.
I have an option called force. In order to create a clock you force a toggle behaviour.
I don't know where create_wave came from or why you're dead set on it?
It's like groundhog day
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What I would recommend is experimenting with records.
See if you like that approach.