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  1. S

    need a book, please help!!

    HI I need the following bbok - Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing: Yannis Tsividis Jose Epifanio Franca if anyone has the link to it, please reply. thanks in advance.
  2. S

    Diffusion area in MOS

    since gate is fabricated before fabricating diffusion regions, and the gate material acts as mask while fabricting the diffusion areas. Please see the 3rd view in any of books, you will find in the 1st or 2nd chapter itself.
  3. S

    Can anybody explain the meaning of this DRC error?

    Re: DRC error this error tells that the space between your substrate contacts is exceeding 30um. generally foundary specifies the distance upto which a substrate contact is effective, in your case it is 30um...i.e some of your devices are placed more that 30um away from the substrate contact...
  4. S

    urgently need this paper..

    M. A. P. Pertijs, G. C. M. Meijer, and J. H. Huijsing, “Precision temperature measurement using CMOS substrate PNP transistors,” IEEE Sensors Journal, vol. 4, no. 3, pp. 294–300, June 2004. Thanks in advance
  5. S

    Oversampling Delta-Sigma Data Converters

    Re: need this book i tried to search in the books section. but was not able to find. if you know the link please let me know. thanks
  6. S

    Oversampling Delta-Sigma Data Converters

    need this book Hi i need this book, if anybody has it then please help... "Oversampling Delta-Sigma Data Converters : Theory, Design, and Simulation" thanks in adavnce
  7. S

    LVDS tx at 1.8v supply - tfall and trise problems

    Re: LVDS tx at 1.8v supply is it prelayout or postlayout. if postlayout then check the parasitic cap present at nodes between switches and current sink/source. if prelayout check the operating region for all the switches and their sat. margins.
  8. S

    LVDS tx at 1.8v supply - tfall and trise problems

    Re: LVDS tx at 1.8v supply check the current? ( of source and sink) are they equal.
  9. S

    need this book Low-Voltage CMOS Log Companding Analog Design

    need this book if any body is having this book, please help? Low-Voltage CMOS Log Companding Analog Design author - Francisco Serra-Graells, Adoración Rueda and José L. Huertas Publication - Springer Netherlands thanks in advance
  10. S

    Error when doing DRC/LVS: "nothing in layout"

    Re: Regarding DRC/LVS? generally the unknown layers( whose gds no. is not defined) are dropped while generating the gdsii with some warning........... hence you can check your report file for this kind of problem.
  11. S

    Error when doing DRC/LVS: "nothing in layout"

    Re: Regarding DRC/LVS? check your layer mapping. it is possible that the layers that you used in layout doesn't correspond to the layers specified in the lvs/drc deck, in that case these layers will be dropped from the layout........and for the deck your gds/layout is empty.
  12. S

    What's the purpose of using filler cells?

    Re: filler cells filler cells are cells that generally contains substrate contacts and ESD circuits. consider the case of memories, in the core array after a number of cells we place these filler cells, they play a very important role here, as core cells are designed for minimum area and even...
  13. S

    substrat contact in std cell

    p substrate can be given below the VDD rail while the n-substrate can be placed below the VSS rail, this is the most preferred way. This saves a area also.
  14. S

    Why dummy transistor requires diffusion instead we can put o

    dummy transister dummy transistors help us in two ways- 1) to fix density errors:- if we have both poly and diffusion min. density error than best way to fix is thrugh dummy transistors, best area utilization. 2) to provide matching to core transistors mainly in analog circuits...
  15. S

    How to use PZ analysis in Cadence tools

    Re: PZ analysis PZ analysis is of use that's why it's present there in tools......... these day's designers don't have time to solve the complete circuit and finds it's poles and zero's..........here this command helps. Instead of wasting a lot of time deriving the transfer function and...
  16. S

    Comparison between Analaog and digital layout

    in digital circuits, there are only two levels - high and low. moreover the transistors work in linear region. while in analog circuits there are no defined logic levels........signal can take any value. Even the transistors work in saturation region. Moreover the analog signals are more prone...
  17. S

    How to equate one terminal to another during Cadence LVS run?

    Re: cadence LVS which tool you are using for lvs. for calibre - there is a option in calibre rve - "connect nets named"...........use this option. same way you would also be having such an option in your tool, just find it. hope this solves your problem.
  18. S

    the spurious signal in ADC

    you can use the FFT or Histogram test methods to calculate the SFDR..........you can also calculate a lot other parameters from these tests like INL, DNL, ENOB, SNR, etc.
  19. S

    How do you calculate electromigration and how to avoid it?

    Re: electromigration electro migration occurs when current density in 1 metal layer is very high.......that can provide electrons flowing through that metal a large amount of energy, thus a electron leaves the metal causing holes.... these holes can lead to open....thus destroying the metal...

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