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  1. C

    help about hspice monte carlo sigma & sweep times

    hspice monte I wonder to know the relation between the sigma & the M-C sweep times. Could you help me?
  2. C

    help about hspice monte carlo sigma & sweep times

    hspice monte carlo Hi, Is there any one giving me a hand about the hspice simulation of the monte carlo sweep times? question : how are the monte carlo sweep times determined? if sigma is 3, must monte carlo sweep times be 1000? if sigma is 5, must monte carlo sweep times be ten million? if...
  3. C

    ESD in silicon integrated circuits

    Re: Help for ESD Protect a taiwan professor website has a good esd lecture.
  4. C

    question about gm/ID=2/(Vgs-Vt)?

    I gree "sutapanaki".
  5. C

    IC voltage doubler and oscillator

    parasitic capacitance make a great effect. and the reverse conduction also have the effect.
  6. C

    Channel Length for Analog Design

    usually >3 Lmin because: 1) process varations 2) output resistor ...
  7. C

    How to connect the 3rd terminal resistor for TEC?

    Re: 3 terminal resistor? It depends on your third terminal pwell or nwell? if pwell,connect vss;if nwell,connect nwell
  8. C

    vddio power line width

    Thanks a lot! Could you tell how much margin will be better?
  9. C

    vddio power line width

    Thanks! But if the IR drop is caculated based on the peak current. It will be very large IR drop. And if the IR drop is caculated based on the average current,the IR drop is accepetable. So how to decide the power width?
  10. C

    vddio power line width

    vddio Hi, the vddio has the big current. So the electromigration and IR drop is needed to considerated. So how to decide to the vddio power line width? So it depends on the average current or peak current? Thanks!
  11. C

    How a substrate connection near source of the CMOS transistor reduces the latch up?

    Re: Regarding LATCHUP It should be many substrate connection. It decrease the resistor. And it also can absorb the minor carrier.
  12. C

    questions about a sturcture to avoid antenna effect in

    when the voltage is very large ,the diode will reverse turn on. it discharge. so the input mos wouldn't be breakdown by the high voltage
  13. C

    How to decide the power bus width?

    Re: power bus width electric migration(average current) : normally 1mA/um IR drop(peak current)
  14. C

    How about these parameters as temperature increase?

    temperature rise => vt decrease, mobility decrease
  15. C

    How to plot a graph Vth vs. Vbs in HSPICE?

    Re: vth vs. vbs let the vth is the x axis,then add the vbs waveform
  16. C

    phase margin of voltage regulator in the nonvolatile memory

    Re: phase margin of voltage regulator in the nonvolatile me Thanks for all of you replies! And I have a new questions: If the precise voltage is be need , the LDO architecture would be used. Is it important for this applications.
  17. C

    phase margin of voltage regulator in the nonvolatile memory

    Re: phase margin of voltage regulator in the nonvolatile me Thanks! I think that PM must be larger than 45 degree.
  18. C

    phase margin of voltage regulator in the nonvolatile memory

    Hi all, Normally, the phase margin is larger than 45 degree. But I heart that the PM of the voltage regulator in the nonvolatile memory can less than 45 degree from my leader. I don't know it's true. If you are the nonvolatile memory designer ,Can you give me the answer ?
  19. C

    Is small phase margin ok ?

    Thanks! It means that the PM maybe become smaller in the silicon results or the other varation conditions. Does it right ?

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