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hspice monte carlo
Is there any one giving me a hand about the hspice simulation of the monte carlo sweep times?
question : how are the monte carlo sweep times determined?
if sigma is 3, must monte carlo sweep times be 1000?
if sigma is 5, must monte carlo sweep times be ten million? if...
the vddio has the big current. So the electromigration and IR drop is needed to considerated. So how to decide to the vddio power line width? So it depends on the average current or peak current?
Normally, the phase margin is larger than 45 degree. But I heart that the PM of the voltage regulator in the nonvolatile memory can less than 45 degree from my leader. I don't know it's true.
If you are the nonvolatile memory designer ,Can you give me the answer ?
Normally the phase margin is larger than 45C or 60. Is it ok if the phase margin is small(for example 30C or 20C) in the regualtor ? Or is it ok that the transient signal waveform is a damped oscillating if only the transient behavior is concerned ?
Thanks for your help!
difference between pn diode and mos diode
I have a question about the difference between the mos diode and the mos parasitic diode(bulk-drain) in the discharge path. why did the mos diode be put in the discharge path,if the pn junction had existed in the discharge path?
I'm design the diff. op with resistive load. And I want to a big gm of input mos.
So I make the w/l very large, but the hspice show the mos into cutoff region.
I'm afraid it doesn't work.
There are ofter 3 stages comparator in the high speed comparator.
They are preamplifer stage,decision stage,output stage.
And I have the 2 questions.
1. What about the specifications for the 3 stages (for example gain et.)?
2. Is there any architechture for decision stage (for example...
I find that the pmos pass element is working at the linear region when the load current is maximum . And I have the following questions:
1. Is it undesirable that the pmos is at the linear region when the load current is maximum?
2. Is the pmos needed to work at the saturation...
Dear all! The capative voltage divider has the low dc current in the level detector.
What is the shortcomings of the voltage divider? And how to design the capacitive the capacitive voltage divider in the level detector?
I need a paper "Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation," IEICE Trans. Electron.,vol E75-C,no. 11,pp.1333-1433,Nov.1922.
The paper is very useful for me. If you can download it ,Please help do it! Thanks a lot!!!
as ad hdif
According to the book,it is necessary to define AS AD PS PD when simulating for transient of hspice. But I think in the model file there is 'hdif' parameter,it can be used as calculate AS AD PS PD.
Hi! I have a question about how to simulate por. what I should choose what kind of
vdd to verify the por? For example, vdd is between 2.5v to 3.6v.
1.what is the min and max rise time and fall time of vdd to use as simulation ?
2.what is rise threshold voltage and fall threshold normally...
I am doing the problems of razavi's book. In the problem 9.18,it says that Vgs3=Vgs5 in order that M5 carries the expected curren when vin=0. why it need to Vgs3=Vgs5 ? what current is "the expected current"? whether it must set Vgs3=Vgs5 in other similar two stage opamps ?
I see a matlab language to load signal from the hspice results,but there are some functions such as 'loadsig,evalsig' which matlab show they are undefined. And my matlab version is 6.5. What's wrong? Can you give the proper matlab language? Thank you!!!
the language is:
% load signals from...