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    List of companies VLSI

    It was really useful............... good work...
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    VHDL Answers to Frequently Asked Questions

    check this link https://www.eda-stds.org/comp.lang.vhdl
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    Simulating congestion control algorithms for Wired and Wireless network using OMnet

    Re: omnet omnet by itself provides simulation samples .It would be a good starting point if u can play around the samples provided by omnet
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    How to configure my internet connection in ubuntu linux?

    it looks probably like ur ethernet drivers are not installed properly.......... Make sure that ur network drivers are installed .. Once its installed, goto the network option in Administration and u can set the IP ..then u can connect to the internet
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    wireless sensor network

    ns2 sensor network u can select the simulators based on the requirements.. If u r new to this , u can go for omnet++ . it would be easier to work
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    VHDL Answers to Frequently Asked Questions

    can u give ur requirements clearly.... What data you require in VHDL
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    Can function be used in Verilog RTL?

    Re: function used in RTL always is a function used in verilog not in VHDL
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    How to connect the FPGA to a PC without using a JTAG cable?

    I have the usb cable to download the bitstream to the fpga. I have used the serial connector of my board to connect to the pc. I don't have a jtag cable to connect my fpga(spartan) to the pc.But i found some softwares which emulate the behavior of jtag.I don't know how to use it also. Is it...
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    Can function be used in Verilog RTL?

    Re: function used in RTL Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit. In VHDL functions can be used, as there is concept of subprograms which comprises of procedures and functions ...
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    How to invoke the Xilinx ISE 8.2i tool?

    Re: Basic Question Follow these steps create a file called YourFile in /usr/local/bin ie( /usr/local/bin/YourFile) copy your settings file to a YourFile export your Display properties to Yourfile export "exec ise" to YourFile Change the permissions of YourFile now you can invoke the tool by...
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    Error when synthesizing in ISE: design is too large to fit the device

    I am able to synthesize my design in ISE9.2i. When i try to implement,it is throwing an error error:The design is too large to fit the device. (In packing phase) how should i make my design to fit into the device
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    Low-power design lessons and reference

    Re: Low-power design Good work Denmos, It is easy to understand and enables the readers to read more Continue posting all the docs reg. low power design
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    porting ise8.2 design in xc4000 series

    i would like to know whether a architecture developed by a later version of ise can be ported to an older series of ise for ex. whether a architecture developed using 8.2i can be ported to xc4003e / spartan xcs10 pls tell me its very urgent..............
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    What is Elaborate in ncsim?

    yes, In synthesis , the term elaboration means converting the rtl code into a generic netlist
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    Anyone help me about SoC Encounter

    But when I use SoC Encounter to read this netlist file it doesn't appear the die size as general i am unable to understand what "die size in general means" .. can you explain exactly what error its showing...
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    difference in real time systems

    can u pls. tell me about MicroCOS II .I know that it is a time deterministic OS ,means a hard real time but sometimes it is called as soft real time why?
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    difference in real time systems

    vxworks ucos interrupt latency what is a hard real time system and soft real system which OS will come under hard real time and which will come under soft real time
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    What is Elaborate in ncsim?

    ncsim cannot elaborate The elaboration process actually constructs a design hierarchy according the information you gave in the design such as the instantiation,configuration ,etc to give the signal connectivity and computes some initial values for all the objects in the design ,which is stored...
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    Transport delay and inertial delay

    what is inertial delay In inertial delay ,the spikes are not propagated to the output whereas in transport delay the spikes are propagated to the output. Usually inertial delays are used for component delays , while transport delay for interconnect delays
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    Differences between Place and Route done in PKS and in First Encounter

    Re: Place and Route pls let me know where should i include the global nets in the PKS synthesis flow

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