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I dont want to use a solder mask in a proto board that i am designing. So if I exclude the solder mask layer when export the layout to a gerber/dxf file, will it ensure that no solder mask layer is used?
I was wondering if someone could provide a comparison of what a pre extraction netlist and a post extraction netlist (with just RC extraction) in terms of the number of parasitic elements that are present in the post-netlist.
Using a certain foundry, we found that the post-netlist had several...
We are going to do two MPWs before engineering lots. What we found was that support from TSMC could be a lot better - even simple questions can take some time. So we are now considering going from TSMC to MOSIS for the MPW for this reason - can anyone comment on the pros and cons of each company...
I wanted to get some thoughts on the impact of parasitics using RC and RCLK extraction for 0.25u and 0.18u.
For 65nm, it seems RC extraction alone could be as much as 20% off of actual silicon performance and here RCLK extraction is preferred. But something tells me that for larger geometries...
Re: LC VCO question
I believe it is the pmos thats causing the voltage to go negative - the negative voltage drives the pmos harder. You can try this out - remove the current source at the top of the pmos and put it below the nmos (instead of its source terminal being connected to ground) - you...
Re: LC VCO question
Can you post a picture of your circuit?
The voltage can go below 0 (as well as above supply) since there is nothing to hard clamp it to ground - negative voltages are sustained by the pmos pair (if the pmos pair was not there, it would not go below 0)
Thanks for your input. I was looking at the pdk kit from xfab and they have all their RF primitive devices (pmos, nmos, varactors etc) with a guard ring around them (vs. putting a guardring around the whole circuit). I am seeing big differences between pre and post...
We have designed a low power VCO and to test it we are bringing out the VCO outputs to be connected to 50 ohm line on a board. We cannot match the VCO output nodes to 50 ohms since this would be too much of a load on the VCO and can affect its frequency and amplitude. So we thought we could...
I was doing simulations on a fully balanced Gilbert Gain mixer - the LO signal is of amplitude 500mV and wanted to see how much of the LO signal leaks on to the RF port.
What I found was that there was very little contribution at LO on the RF port but there was a huge component at 2LO on the...
Phase noise plots for oscillators using Cadence spectre (PSS+PNoise) in dBc/Hz show noise values greater than 0 at close in frequencies to the carrier (including several plots in their user guide)
How is this possible?
Thank you for your input. With a channel spacing of 100kHz, Loop bandwidth say is 10kHz. This means that the settling time taking approx. 10/LB = almost 1ms. This is a little too much time for the application.
I am wondering if there are things that can be done to speed up the lock...
I am trying to design an integer n pll for 915MHz with a channel spacing of 100kHz. I wanted to get a sense of what are possible lock times possible. Is a lock time of say 100us feasible at all?
Thank you in advance