Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. D

    Help me reduce the variation of the ring VCO output

    ring vco I'll try and find out. Thanks.
  2. D

    Help me reduce the variation of the ring VCO output

    ring voltage controlled oscillator The temperature is fixed, default 27 degrees. The process model is typical and is fixed in the simulation, so the variation of the output waveform doesn't result from the model changing from 'slow' to 'fast'. And the power supply is also fixed. In a short, all...
  3. D

    Looking for license for @ns0ft En$emble8.0

    Where can I get?
  4. D

    Help me reduce the variation of the ring VCO output

    ring vco Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys...
  5. D

    Frequency synthesizer test?

    I'm working on a 900MHz PLL-based frequency synthesizer. I wonder if anybody can give me some advice on the testing of the frequency synthesizer (such as test machines, test set-up block diagram, etc.)?

Part and Inventory Search

Top