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Our Sensors encounter many EMC problems at the customer end.
For example, we can be sure of the correctness of the chip output sync signal, data, and clock. But our customers do the PCB design themselves when incorporating our sensors into their systems. Many times they...
How to prevent digital swithcing noise from disturbing analog circuits?
Should I use Deep N-well to envelop all digital circuits as someone's advice?
Or envelop all analog circuits?
any other methods to deal with the noise between digital and analog?
Thanks in advance
Anyone knows how to pause a hspice simulation?
Also, I sometimes need pause a simultion, shut down the machine, restart the machine several hours later, then go on the paused simulation from the break point. Is it possible?
I have a band gap, which is implemented with TSMC018 Process 5x5 pnp transistors. With the circuit I get 1.265v bandgap output.
But when I shift it to Tower018 Process, I can only get 1.136v output.
I test the Vbe temperature coefficient, and find that the coefficient is smaller than TSMC pnp5x5...
I designed a bandgap and hspice simulation showed that it's output=1.25v.
Then I layed out it and did lvs, passed. Then I extracted netlist including parasitic R and C from the layout with xcalibre, simulated again and found that its output=1.8v (power supply).
Firstly, I thought the parasitic...