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  1. A

    configuring Logic Bist, how can it be desceased or increased

    logic bist Hi, How can we configure the clock at which the LBIST runs?How can the clock for BIST be either decreased or increased?
  2. A

    What is pin strapping and what is it used for?

    Hi, I would like to know, what is pin strapping and what it is used for. If it can be used for configuring fpga or cpld how it is done?
  3. A

    slow to fast synchronization

    Asynchronous fifo can be used for synchronization. Basically i wanted to know any other synchronization technique apart from using fifo. We have handshake based synchronization in the case of data transfer from fast domain to slow domain. But can the handshake synchronization be used for...
  4. A

    slow to fast synchronization

    If I have data(multi bit) to be transferred from a slow clock domain to fast clock domain, then what kind of synchronization technique can be applied. Say if sending clock period is 30 ns and receiving clock period is 5 ns then the data will be sampled for atleast 5 cycles in the receiving...
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    synchronous reset or asynchronous reset?

    asynronous reset asynchronous reset should be insteadof synchronous reset as synchronous reset results in more gates. Hence asynchronous reset must be used and it shoudl be synchronized. Usually reset synchronization is done such that the assertion of reset wil be left asynchronous but...
  6. A

    Best book to learn Verilog?

    learn verilog Advanced Digital Design with the Verilog(TM) HDL by Michael D. Ciletti
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    what is a transparent latch?

    yes both are same. Latch is said to be transaparent as it gives the same output as the input as long as there is enable to the latch is high.
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    How to do functional coverage using NCVHDL and System Verilog?

    Re: functional coverage I have actually done functional coverage for verilog desing using system verilog. Ncverilog supports system verilog. The same thing I want to do for my vhdl design. I have gone through ncvhdl docs and found that system verilog constructs are not supported. Do I have to...
  9. A

    How to do functional coverage using NCVHDL and System Verilog?

    how to do functional coverage using ncvhdl and system verilog. Does ncvhdl support system verilog constructs?

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