Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am writing RTL for a module, which interfaces with a different chip on the platform.
As part of the flow, this hardware module needs to do 10 register reads from the third party chip.
Read flow is =>
Module writes address, valid and rw signals on the first cycle and the...
4 bit wide data bus needs to be transferred into slow clock domain. Sending clock is 100Mhz and receiving clock is 50MHz. The two clocks are synchronous clocks (clocks are derieved from the the same PLL). The 4 bit data changes every write clock cycle.
How to do a CDC without using FIFO?
Recently I had this question in an interview.
Request is 1 bit input to the DUT and grant is 1 bit output from the DUT. Design is when request goes high, ack has to follow request and should go high within 64 cycles. Similarly when request goes low, ack should go low within...
How should I understand input and output impedance in general? For example, the input impedance of an amplifier is this much and output impedance is this much. And what does that imply?
Say, input impedance of hte amp is very low/very high. And how does that matter when I design my...
linear amplifier design
when we say an amplifier is linear? Is it linear when gain is independent of the input voltage level?
Do we have any other metrics to qualify an amplifier as a linear one?
Highly appreciate your inputs.
The concept of input CM in differential amplifier is unclear. Is this CM is DC CM or AC CM? When we apply an ac signal to the diffrential amplifier What is the CM voltage? Is this the offset from 0 or do we have to look this with refrerence to differential signal ? Please explain the...
Generally it has been mentioned that when high gain amplifier has to drive a low impedance load the usage of voltage buffer ( high i/p impedance and low o/p impedance) is recommended. Please explain me the logic behind this. Why we can not directly connect a high impedance load...
Usually MOS amplifier are always analysed with respect to its input and output impedance. But I am unable to relate this with the understanding of the MOS amplifiers.
LIke. Whether i/p impedance or o/p impedance should be low or high..
How the impedance will affect...
In MOSFET small signal models, analysis are being carried out when Substrate, gate and drain are at ac ground. Though I could able to understand what dc ground is, ac ground seems to be puzzling.
Will highly appreciate if analog veterans can throw some light on this...
As a fresh VLSI design engineer..I am finding it very difficult in getting calls for entry level positons from companies..People say that usually guys are called for written tests only through referrals!! After applying for the last 2-3 months I am also feeling the same..Guys...