Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. A

    digital interview questions with answers?

    That's always difficult to find answers to asic/fpga digital design interview questions. Following site has a decent collection of design questions and answers or hints to links to find complete answers. https://www.fullchipdesign.com/interview.htm
  2. A

    clock gating - implementing ICG cell

    this link has more details **broken link removed**.
  3. A

    clock gating - implementing ICG cell

    AND gates can result in glitches, so not recommended. But if you think design can handle the glitches then you can do an eco in synthesized netlist or change in rtl to insert a AND gate and then make appropriate connections.
  4. A

    [PLL] What is free running clock

    Free running clock is not part of any standard. This is just a way of showing the independence in phase relationship of a clock on a chip to other clocks. The PLL's on chip can used free running clocks as input to generate fixed output clocks. This link has details on PLL.
  5. A

    plz help me i hate to submit before 30th of this month

    See if this gives you some background to solve the problem shift_logical_circular_arithmetic
  6. A

    How to drive FRIIS equation for cascaded Noise factor calculation?

    How to drive FRIIS equation for cascaded Noise figure calculation? I know the formula to calculate cascaded noise factor Ftotal = F1+(F2-1)/G1+ (F3-1)/(G1G2)
  7. A

    Gate Level Simulation: Delay or No Delay?

    Delays are required on IP/RTL models involved in gate-level sims. These Verilog #delays insert required routing delays on actual (hardware) paths.
  8. A

    [SOLVED] Sate assignment VHDL versus Verilog

    Lets use example at this link The case statement at that link can be modified to use parameters // Declare parameters soon after Inputs/Outputs declaration parameter S1 = 10, S2= 11,S3 = 12, S4= 13, S5 = 14, S6= 15; // Replace the values with parameters case (r_count) S1 : begin...
  9. A

    clock gating - implementing ICG cell

    Most of the clock gating cells from libraries will have a module instance (Verilog) that you can instantiate in your source code. Most likely the module will have three inputs (clk, clk_en and test), one output port (clk) for gated clock.
  10. A

    Full chip design flow

    Most of the EDA flows follow 5 step approach Synthesis, pin map/ IO ring insertion, constraints, place - route and static timing analysis. The details can be found at **broken link removed**
  11. A

    FIFO Depth Calculation

    Burst means back to back reads without any idle clock cycles.
  12. A

    FIFO and their architectues

    FIFO is a standard arch of First in First Out, but there are different archs for data storage .. check these links out FIFO **broken link removed**
  13. A

    FIFO Depth when READ Frequency is < WRITE Frequency

    You can design a efficient FIFO with appropriate depth to work in a scenario where read clock frequency is lower write clock frequency. There is a good reference: http://fullchipdesign.com/fullchipdesign_ext.htm
  14. A

    FIFO Depth Calculation

    There is simple explanantion at https://www.fullchipdesign.com/fifodepth.htm

Part and Inventory Search