Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. S

    Small signal model CMOS !!

    The internal resistance of an ideal current source is infinite. An independent current source with zero current is identical to an ideal open circuit.
  2. S

    Overdrive voltage understanding

    Hi Viper, Consider the case of current mirror (One MOS diode connected, providing VGS to other MOS), in reference branch the reference current is say 1uA. than what will be its overdrive voltage (Say Vth=600mV). Here we need to know what is W,l of MOSFET. Say for a particular W,L if...
  3. S

    Queries : PFM mode Stability Analysis in DCDC converters.

    I got answers up-to some extent, sharing for others. 1. PFM mode loop is open loop or close loop? Ans: Close Loop. 2. Can we model the PFM loop? Ans: Yes, we can model the PFM loop using state-space averging method. Its bit complex as involved algebra. 3. Is it required to do Stability...
  4. S

    Queries : PFM mode Stability Analysis in DCDC converters.

    I didn't get your point. "System is not present" means what ? PFM loop consist of: Res div feedback, Max current detect block, Zero current detect block, Comparators along with PowerFets, L & C etc. Please Consider PFM loop as closed loop. Correct me if I am wrong.
  5. S

    Queries : PFM mode Stability Analysis in DCDC converters.

    Please explain in terms of stability analysis. That will be helpful . - - - Updated - - - Yes, for PWM mode Stability analysis is required. Please explain the necessity of stability analysis in PFM loop.
  6. S

    Queries : PFM mode Stability Analysis in DCDC converters.

    1. PFM mode loop is open loop or close loop? 2. Is it required to do Stability Analysis for PFM loop ? If No Why ?
  7. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Okay Lvw, I will think on your comments (should give some time on CD stage). Thanks for your time and consideration.
  8. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Hi LvW, Yes, certainly I am missing some point about CD stage amplr. That`s why I am discussing it here. Thanks for being patience with my doubts. So now for CD stage if you are Saying...
  9. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Hi LvW, So In case of CS stage Av= Gm * rout Is it correct ??? If yes then Av = gm1 * (r,load||ro1); with r,load=ro2 we have Av=gm1*ro/2 Here my point is : rout = (ro2||ro1), is used in gain...
  10. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Hi LvW, Thanks for your explanation. Considering your answer "Av=Gm*Rs" is correct. I am getting one more doubt. So I would like to ask same question in terms of CS stage amplifier with pmos...
  11. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Yes, So can I say if r,out=Rs||(1/gm) & Gm = gm/(1+gm*Rs) Then Gain Av= Gm*r,out Av = gm/(1+gm*Rs) * Rs||(1/gm) = gm/(1+gm*Rs) * Rs/(1+gm*Rs) = ( gm*Rs)/(1+gm*Rs)^2 But CD stage Gain...
  12. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    Re: What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifie Hi LvW, Please specify the Gm & Rout in the gain formula. Are you saying Rout = Rs || (1/gm) = Rs /(1+gm*Rs) is not correct ?? & Gm = (gm)/(1+gm*Rs) is correct ? Please reply.
  13. S

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier Hi All, What will be the expression of Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier. Here Gm is trans-conductance of the amplifier. If over all gain Av = (gm * Rs ) /(1+gm*Rs) &...
  14. S

    Gain derivation of pmos amplifier

    I think the gain will be : gmx1 * ((1/gmx3) || (rdsx7) || (rdsx1)) Which on approximating Gain = gmx1* (1/gmx3) = gmx1 / gmx3
  15. S

    Low Dropout Regulator Design

    Hi Navid, You should broke each loop one by one and do stability (AC) analysis for it. For LDO stability both loop should be stable.
  16. S

    UGB Gain & Phase Margin

    Hi Nikhil, Considering that you have only two poles inside UGB. UGB can be decided by gain & first dominant pole location. Ex: For high BW (600MHZ, your other post) your pole should be far from origin. Now for Phase Margin >30deg <45deg your 2nd pole location should be close to...
  17. S

    Please Help Single Ended Folded Cascode

    UGB>600MHz is very tough to achieve. Please specify the pole locations.
  18. S

    ac & dc isolation in amplifier circuit

    Hi Disha, In case of Amplifiers say single-CS-stage (MOS) amplifier. Once we bias the opamp in saturation region. The simulator makes an linear-model of mosfets (opamp) and apply ac signal over it. So now even if we change the ac signal amplitude say 1V, the Mosfets will not see...
  19. S

    Biasing CMOS analog design

    Hi Chirag, As u need good output swing, you can go with Low voltage Cascode Current Mirror circuit mention in Razavi. One more point : In your circuit How You are generating gate bias for your PMOS tail current mirrors. It looks like your PMOS (diode connected 3rd branch) is off.
  20. S

    Drain with large amplitude

    Hi Praveen, Say you made Vgs(500mV) -VT(400mv) =100mv Then as long as your drain voltage is greater than 100mv Your Mos will be in saturation region. for ) to 100mv it will be in triode region. For NMOS: Vds=> Vgs-Vt for Saturation

Part and Inventory Search

Top