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Hi erikl. But in NAND for the upper NMOS, the body(p substrate) should be connected to source right?
I feel i am lost here.
I have these doubts.
is the p substrate not the body or bulk of the NMOS?
also nwell not the body or bulk of the PMOS?
Iam drawing a layout in Cadence for a 2 input nand gate.In the Pull down network i used a p substrate for each of the NMOS. For the lower NMOS i connected the substrate to Ground.But, when i connect the substrate of the upper NMOS to the its source as in the schematic,i get the errors
Yes the mistake was with declarations.i declared the variables i,j as one bit register instead of 2 bits.So, the loop for j never closed.Anyway thanks.
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Im a beginner in verilog.It was a problem with declaration.I tried your code too.Thanks for the help.
This is the part of my code for histogram segmentation. It has to read data from in[i][j] into a temporary variable n which is the intensity of that pixel.Then it has to increment the nth bit of the hist vector by 1 so that at the end the vector hist has the requires histogram values.But the...