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    Start/Stop Counter Using Finite State Machine (Verilog)

    I don't know whether I can do it or not, but I was thinking to generate the start/stop signal after the analog digital conversion. I'm using two channel ADC for two analog sensors. Sensors give maximum output while at rest, and when an object comes, the output voltage decreases. So I thought...
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    Start/Stop Counter Using Finite State Machine (Verilog)

    This is my code for the state machine. I used the output signal CountEnable to enable my counter. I also simulated this state machine with the counter i think it counts fine, but i have some "ripples" between some values while counting which seems not effecting the count value and i don't know...
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    Start/Stop Counter Using Finite State Machine (Verilog)

    Hi, I'm trying to design a counter using finite state machine, with a start and a stop input. as output, I need the count value for calculating the time between start and stop signals. I calculated my max. count value as 90000, 17 bits (90 ms, with 1 MHz clock frequency). By the way I'm not...
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    [SOLVED] About DE0-Nano Board Configuration Device

    Hi, I have a DE0-Nano Board and when i turned its power off after programming then turned on again, it always loaded its default program. The user manual says that even the power is turned off, the information is retained in the configuration device (Spansion EPCS64). So, everytime i turned its...
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    [SOLVED] SPI slave module question

    I'll try that. thank you very much.
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    [SOLVED] SPI slave module question

    okay, so i can count the sent data as the received one? what about this slave select part? i couldn't quite understand the purpose of SSEL_startmessage and SSEL_endmessage. i mean when the SSEL is active, isn't it always zero after it's activated? reg [2:0] SSELr; always @(posedge clk) SSELr...
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    [SOLVED] SPI slave module question

    Hi, i'm working for a SPI slave module on fpga with verilog. I have not used SPI before, so i don't know it well. I just read and looked some examples about it. http://www.fpga4fun.com/SPI2.html -> on this website it's very simple i think. but there are some points i couldn't understand. in...
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    [SOLVED] Rising Edge Detector Synchronization Problem

    yes, i'm using quartus simulator. i'm new to designing in HDL and i don't know whether the results are correct. because in the examples i looked up, the output pulse (sync_clk) toggles as the input signal (sign_in) goes up. like in this one http://fpgacenter.com/examples/basic/edge_detector.php
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    [SOLVED] Rising Edge Detector Synchronization Problem

    hello, i designed an edge detector in verilog. it's RTL seems correct, but in simulation the output pulse is delayed. The examples on the internet, the pulse starts exactly with the rising edge of the clock signal. i used no delay in simulation. capture from the simulation and the code module...
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    by the way, thanks all for your help. i managed to see my design works well. i set the end time for the simulation by Edit > End time.
  11. H

    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    and my simulations always stop at about 1 us. whether or not i specify the "end simulation at: " time, it always stops at the same value. so i can only see one transition for the divided clock cycle.
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    this is the current divider module. but i didn't use a testbench, i tried to use the simulator within the quartus 2. i don't know how to write a testbench yet so just used the simulator tool with a vector waveform file. // Clock divider circuit // From 50 MHz to 1 MHz/200 Hz with %50 duty cycle...
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    and another simple question about simulator: i've tried to run the simulation for 10000 ns as you suggested by selecting "end simulation at: " setting, but it still shows only one transition of the divided clock signal, for 1 us. any suggestion about that would be appreciated?
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    okay, thanks for the answer and now i have another question. in the simulation report, when i look the output clock period it's 995,66 ns, the first half is 495,66 ns and the second half is 500 ns. what's causing this difference? because i got the same result when i design the divider with vhdl.
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    hi, i'm new to the forum and FPGA. i'm designing a simple clock divider from 50 MHz as parameterized for a small part of a project. my code is successfully compiled but when i try to simulate it with quartus timing analyzer, the output clock is all X. i suppose there's something wrong with the...

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