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    Xilinx CPLD XCseries power

    Hello , can u please give me some info regarding , what way is there to find the maximum that a CPLD takes (XILINX) 1) How does the Power (the maximum) consumed by a CPLD (preferably Xilinx) i have gone through the Google , for the same and also the vendor's site , the terms were confusing...
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    vlsi design tools- description, basic tools, good websites

    vlsi design tools Hi Can anyone please tell me what exactly can we do with the Cadence , virtuso , and other tools. 2) what are the basic tools one should know, if , one wants to his career with the VLSI design. 3) Can u please suggest some good sites that give an overview of different...
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    Tools : Cadence, virtuso, cadstar etc , etc.

    Hi Can anyone please tell me what exactly can we do with the Cadence , virtuso , and other tools. 2) what are the basic tools one should know, if , one wants to his career with the VLSI design. 3) Can u please suggest some good sites that give an overview of different tools for different...
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    communication problem between two FPGA board through UART

    UART -help Hello , I m trying to communicate between two FPGA board through UART , a constad data of 16 byte is being transmitted from the board1 with a baudrate say 9600. and the other board is also configured to receive at the same baud rate, i m trying to receive the 16 bytes of data and...
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    need CPLD tools to practise or synthesis tools

    CPLD tools ?? Can anyone suggest the best tools to practise or to look for a LATTICE CPLD / any synthesis tools for CPLD ???
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    AES CORE (128/192/...) URGENT ! PLS

    Can anyone help me with an AES core (128/256) , other than from opencores? or if from open cores , help me in how to extract the files . Thanks in advance
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    AES Application - ACTEL FUSION FPGA- 40 points for help

    actel fusion Hello I m currently interested in coming up with a Small application based on AES to implement and verify through ACTEL FPGA - Fusion device. How one can show the encryption and decryption ? Can anyone give me some more idea as i am a lay man regarding this. Please do help...
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    Post synthesis Vs pre synthesis

    post synthesis simulation pre synthesis Hi all ! How was the weekend ..? Can you please explain : 1) what exactly happens during pre-synthesis simulation and post synthesis simulation? (Netlist generation etc etc is ok , i need something in detail) 2) what care one should take while coding...
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    Pruning instances ?? -SYNplify

    pruning register synplify why does the synthesizer prune certain instances when instantiated ?what actually does this pruning pertain to in a synthesizer. when the synthesizer prunes a register/an instance , will the design work as expected? can anyone throw more light on the same ..?
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    Newbie to ASIC DESIGN - need suggestions

    NEWBIE TO ASIC DESIGN Can anyone suggest how to start my preparation for updating myself to ASIC DESIGN concepts . I have 1 year of exp working in applications involving Mixed signal FPGA , programming in VHDL .
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    Alternative for if-elsif. please Discuss your opinions .

    hello , i have to read from a memory location say 10 x8 location , which i term as Vector. Can anyone suggest me an alternative way of reading those vector locations at some different counts. say at every 120µs,125µs,130µs,220µs,225µs,250µs,...... at different 32 time slots. for example in...
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    Initialisation of Array in VHDL

    create a array of hexadecimal numbers in vhdl type VECTOR_MEM is array (23 downto 0) of std_logic_vector(9 downto 0); -- 8x8 signal INSTR_VECTOR : VECTOR_MEM; -- 24 X10 locations. can anyone please tell me how to initialise these values with a predefined set of vectors. -- while accessing...
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    Case -when statement-VHDL

    vhdl case statement when using the case statement for , it displays when others condition is not synthesized. is there any alternative for this . <code> f (STROB1= "01")then ADC_DATAMOS_TEMP <= ADC_DATAMOS; else ADC_DATAMOS_TEMP<= "ZZZZZZZZ"; end if ; process...
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    Multiple non-tristate drivers for net -Urgent Help

    multiple non-tristate drivers for net library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity SEQUENCER is port ( CLK_SEQ : in std_logic; RST_SEQ : in std_logic; RW : out...
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    RTL Vs Structural style of VHDL coding .

    structural vhdl Hi .. ! can anyone please tell me the importnat differences between RTL and structural style of coding .? are they same or different ? In what way they do differ with other styles? .? And also as far an ASIC design is considered what are the major differences . Thanks in...
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    RTL Vs Structural style of VHDL coding .

    Hi .. ! can anyone please tell me the importnat differences between RTL and structural style of coding .? are they same or different ? In what way they do differ.with each other .? And also as far an ASIC design is considered what are the major differences . Thanks in advance >[/b]

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