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  1. M

    how to calculate cache size

    how to calculate cache size?
  2. M

    what is a zero phase filter

    what is a zero phase filter how to design it in matlab?
  3. M

    filter transfer function (s+w)/s ?

    what does this transfer function (s+w)/s mean for a filter?
  4. M

    how to design an 8-bit sigma delta ADC

    At the output we get 1-bit data stream, how can it be 8-bit? thx
  5. M

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received at port1 or port2 and deliver them in the same order at port3. Assume that each data word is 8-bit wide. The external systems that provide data at port1 and port2 use the sender originated protocol and the...
  6. M

    • Give me an example of asynchronous finite state machine

    • Give me an example of asynchronous finite state machine
  7. M

    List all possible ways to minimize the power dissipation of an ASIC chip

    List all possible ways to minimize the power dissipation of an ASIC chip Thx
  8. M

    verilog code for intel 8085 processor

    who can give a verilog code for intel 8085 processor?
  9. M

    design a 8 bit processor with the following specifications

    Design a 8 bit processor with the following specifications1: 1. The processor has seven 8-bit registers A, B, C, D, E, H and L. 2. It connects with an external memory containing 32 8-bit words. The memory has a tristate output with active low signals rd and wr. 3. It has instructions MOV, LDA...
  10. M

    why no clock and reset signal

    `timescale 1ns/1ns module test_project1; reg clk,reset; reg [7:0] port1; wire [8:0] port2; integer file; initial file=$fopen("proj.dat","rb"); always@(posedge clk) $fscanf(file,"%d",port1); initial begin clk = 0; reset = 0; reset = #1 1'd1; reset = #2 1'd0...
  11. M

    syntax error, unexpected wire, expecting";"

    Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong? code: module test_project1 wire clk,reset; reg [7:0] port1; wire [8:0] port2; reg eof; integer project1; initial project1=$fopen("proj.dat","rb"); always@(posedge clk) begin eof=feof(project1)...
  12. M

    Whats inside a FLASH and its operation?

    Whats inside a FLASH and its operation?
  13. M

    How to do a frequency divider on FPGA

    How to do a frequency divider on FPGA
  14. M

    if the input of an inverter is floating, what would the output be

    if the input of an inverter is floating, what would the output be

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