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  1. J

    fpga implementation of circuits having clock

    if we want get a pattern that is changed in ach clock cycle, how can we run in spartan 3E fpga kit. plz reply
  2. J

    accumulator based pattern generation

    what is the method of generating test patterns in accumulator based weighted pattern generator. What is the use of session counter
  3. J

    how to write the ucf file in xilinx for array variables

    in the main program i have some output variables which are declared as array. ex: chain1, chain2:out array Each bvariable stores 7 bits.ie: chain[0] to chain [7] and similarly for chain2. If we use std_logic_vector , in ucf file we can write it as NET "chain<0>" LOC "p23" NET "chain<1>" LOC...
  4. J

    gate count in the synthesis report in xilinx

    During synthesis in xilinx, i got number of slices,slics flip flop, 4 input LUT's, bonded IOB's GClk's. How can i get the number of gates. plz reply
  5. J

    how to write the ucf for clock signal

    how to write the ucf for clock signal if there are 2 clock signals for spartan 3E fpga kit. the pin number of one clock is p122. How can the other clock signal can be included. plz reply
  6. J

    Expanded RTL view and technology view in xilinx

    How to view the Expanded RTL view and technology view in xilinx
  7. J

    how to write ucf file in xilinx for vhdl code for an std_logic_vector

    How can we write a ucf file in xilinx. I want to take 8 bit patterns as output. There are 16 such patterns. In each clock one 8 bit pattern is given to output. How an std_logic_vector can be coded in an ucf file. plz reply
  8. J

    vhdl code for copying an array of elements

    I have an array variable 'choice'. It stores an array of 8 bit elements. I want to transfer each 8 bit element to another variable 'vector' in each clock transfer. This is repeated until the count 'ctt1' becomes 17. But in each transfer only first 4 bits are transferred and remaining 4 are uuuu...
  9. J

    vhdl code fordivision whose result is a floating point number

    whether floating point division in vhdl is possible. if possible is there any simple program or keyword for that. plz explain
  10. J

    ISCAS Benchmark circuits

    who owns ISCAS Benchmark circuits (ISCAS 85 and ISCAS 89). plz reply .
  11. J

    VLSI jobs in european countries

    what about the vlsi job oppurtunities in countries like canada, us, australia, new zealand, switzerland, singapore. whether ielts necessary for engineering jobs in thesse countries. is there any website that helps for job hunting. can we directly apply for such jobs from india
  12. J

    networking courses ccna,ccnp etc

    can anyone give me some idea abt networking courses ccna, ccnp etc. which one is better for jobs. whether it can be self studied. what about the networking job oppurtunities in middle east countries. i am a ME VLSI graduate. Is networking course helpful for me. whether there is any vlsi job...
  13. J

    s344 benchmark circuit

    can anyone explain the working of s344 benchmark circuit.In fault detection ,during simulation whether we use only beenchmark circuit.can we use normal full adders etc.whether s344 detects a single stuck at fault
  14. J

    Cadence for fault coverage

    whether fault coverage calculation is automatically possible in cadence
  15. J

    Mentor graphics flex test

    how can we use mentor graphics flex test
  16. J

    mentor graphics flex test

    what is mentor graphics flex test.plz reply
  17. J

    project internship for ME final year

    can you suggest some companies where ME project internship is available.plzz reply
  18. J

    fault coverage detection

    i want to generate some test patterns and applied to a circuit.How the fault coverage is detected.plz reply
  19. J

    one dimensional array in vhdl

    How can i store values in a ID array, if each location store multiple bits. ex:[1001, 1010,1111] These number of bits and number of locations are variable.The values stored are the output of a variable length circuit which can be set by the user. plz reply
  20. J

    fault coverage calculation for test patterns

    whether fault coverage of test pattern can be found out using cadence tool.How is it calculated.

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